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Hitachi SuperHTM RISC engine
SH7018
Hardware Manual
ADE-602-186 Rev. 1.0 3/4/03 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Preface
The SH7018 is a single-chip RISC (reduced instruction set computer) microcomputer with a CPU based on Hitachi-original RISC-type SuperHTM* architecture as its core. It also provides peripheral functions essential to system composition. The CPU incorporated into the chip supports the RISC instruction set. Basic instructions execute in one cycle (one system clock cycle), so instruction execution times are extremely fast. The chip has an internal 32-bit architecture for efficient data processing. The CPU is capable of supporting applications employing real-time control. Such applications were not practical using previous microcomputers due to the extremely fast processing speeds required. It makes possible the development of systems providing high performance and excellent functionality at low cost. The chip incorporates several peripheral functions essential to system composition, such as ROM, RAM, timers, serial communication interface (SCI), A/D converter, interrupt controller (INTC), and I/O ports. It also supports external memory access, which allows for efficient connections to external memory and LSI devices. These features help to reduce system costs substantially. The SH7018 employs on-chip flash memory with F-ZTATTM* (flexible zero turnaround time). In addition to allowing programming of the chip by writing to it using a program writer for LSI devices, software can be written to the flash memory and erased as necessary. This Hardware Manual describes the hardware features of the SH7018. For detailed information on the supported instructions, please refer to the Programming Manual. Note: * SuperHTM and F-ZTATTM are trademarks of Hitachi, Ltd. Related Manuals SH-1/SH-2/SH-DSP Programming Manual. For information on development environment systems, please contact a Hitachi sales office.
Contents
Section 1 SH7018 Overview ............................................................................................ 1
1.1 1.2 1.3 SH7018 Features................................................................................................................ 1 Block Diagram................................................................................................................... 5 Pin Description .................................................................................................................. 6 1.3.1 Pin Layout ............................................................................................................ 6 1.3.2 Pin Functions........................................................................................................ 7
Section 2 CPU ....................................................................................................................... 11
2.1 Register Configuration ...................................................................................................... 11 2.1.1 General Registers (Rn) ......................................................................................... 11 2.1.2 Control Registers.................................................................................................. 12 2.1.3 System Registers .................................................................................................. 13 2.1.4 Initial Values of Registers ................................................................................... 13 Data Formats...................................................................................................................... 14 2.2.1 Data Format in Registers...................................................................................... 14 2.2.2 Data Format in Memory ....................................................................................... 14 2.2.3 Immediate Data Format........................................................................................ 14 Instruction Features ........................................................................................................... 15 2.3.1 RISC-Type Instruction Set ................................................................................... 15 2.3.2 Addressing Modes................................................................................................ 18 2.3.3 Instruction Format ................................................................................................ 22 Instruction Set by Classification........................................................................................ 25 Processing States ............................................................................................................... 38 2.5.1 State Transitions ................................................................................................... 38 2.5.2 Power-Down State................................................................................................ 39
2.2
2.3
2.4 2.5
Section 3 Operating Modes ............................................................................................... 41
3.1 3.2 3.3 Operating Mode Selection ................................................................................................. 41 Description of Operating Modes ....................................................................................... 41 Pin Configuration .............................................................................................................. 42
Section 4 Clock Pulse Generator (CPG) ....................................................................... 43
4.1 4.2 Overview............................................................................................................................ 43 Clock Source...................................................................................................................... 43 4.2.1 Crystal Resonator Connection.............................................................................. 43 4.2.2 External Clock Input ............................................................................................ 45 Usage Notes ....................................................................................................................... 45
4.3
i
Section 5 Exception Processing ....................................................................................... 47
5.1 Overview............................................................................................................................ 47 5.1.1 Types of Exception Processing and Priority ........................................................ 47 5.1.2 Exception Processing Operations ......................................................................... 48 5.1.3 Exception Processing Vector Table...................................................................... 49 Resets................................................................................................................................. 51 5.2.1 Reset ..................................................................................................................... 51 5.2.2 Power-On Reset.................................................................................................... 51 Address Errors ................................................................................................................... 52 5.3.1 Address Error Exception Processing.................................................................... 52 Interrupts............................................................................................................................ 53 5.4.1 Interrupt Priority Level......................................................................................... 53 5.4.2 Interrupt Exception Processing ............................................................................ 54 Exceptions Triggered by Instructions................................................................................ 54 5.5.1 Trap Instructions .................................................................................................. 55 5.5.2 Illegal Slot Instructions ........................................................................................ 55 5.5.3 General Illegal Instructions .................................................................................. 55 When Exception Sources Are Not Accepted..................................................................... 56 5.6.1 Immediately after a Delayed Branch Instruction.................................................. 56 5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 56 Stack Status after Exception Processing Ends................................................................... 57 Notes on Use...................................................................................................................... 58 5.8.1 Value of Stack Pointer (SP).................................................................................. 58 5.8.2 Value of Vector Base Register (VBR) ................................................................. 58 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 58
5.2
5.3 5.4
5.5
5.6
5.7 5.8
Section 6 Interrupt Controller (INTC) ........................................................................... 59
6.1 Overview............................................................................................................................ 59 6.1.1 Features ................................................................................................................ 59 6.1.2 Block Diagram...................................................................................................... 60 6.1.3 Pin Configuration ................................................................................................. 61 6.1.4 Register Configuration ......................................................................................... 61 Interrupt Sources................................................................................................................ 62 6.2.1 NMI Interrupts...................................................................................................... 62 6.2.2 IRQ Interrupts ...................................................................................................... 62 6.2.3 On-Chip Peripheral Module Interrupts ................................................................ 63 6.2.4 Interrupt Exception Vectors and Priority Rankings ............................................. 63 Description of Registers .................................................................................................... 66 6.3.1 Interrupt Priority Registers A to H (IPRA to IPRH) ............................................ 66 6.3.2 Interrupt Control Register (ICR) .......................................................................... 67 6.3.3 IRQ Status Register (ISR) .................................................................................... 68 Interrupt Operation ............................................................................................................ 70
6.2
6.3
6.4
ii
6.5
6.4.1 Interrupt Sequence................................................................................................ 70 6.4.2 Stack after Interrupt Exception Processing .......................................................... 72 Interrupt Response Time.................................................................................................... 72
Section 7 Bus State Controller (BSC)............................................................................ 75
7.1 Overview............................................................................................................................ 75 7.1.1 Features ................................................................................................................ 75 7.1.2 Block Diagram...................................................................................................... 76 7.1.3 Pin Configuration ................................................................................................. 77 7.1.4 Register Configuration ......................................................................................... 77 7.1.5 Address Map ........................................................................................................ 78 Description of Registers .................................................................................................... 80 7.2.1 Bus Control Register 1 (BCR1)............................................................................ 80 7.2.2 Bus Control Register 2 (BCR2)............................................................................ 82 7.2.3 Wait Control Register 1 (WCR1) ......................................................................... 86 Accessing Ordinary Space................................................................................................. 88 7.3.1 Basic Timing ........................................................................................................ 88 7.3.2 Wait State Control................................................................................................ 89 7.3.3 CS Assert Period Extension.................................................................................. 91 Waits between Access Cycles ........................................................................................... 92 7.4.1 Prevention of Data Bus Conflicts ......................................................................... 92 7.4.2 Simplification of Bus Cycle Start Detection ........................................................ 93 Memory Connection Examples ......................................................................................... 94
7.2
7.3
7.4
7.5
Section 8 Multifunction Timer Pulse Unit (MTU) .................................................... 95
8.1 Overview............................................................................................................................ 95 8.1.1 Features ................................................................................................................ 95 8.1.2 Block Diagram...................................................................................................... 98 8.1.3 Pin Configuration ................................................................................................. 99 8.1.4 Register Configuration ......................................................................................... 100 MTU Register Descriptions............................................................................................... 101 8.2.1 Timer Control Register (TCR) ............................................................................. 101 8.2.2 Timer Mode Register (TMDR) ............................................................................ 105 8.2.3 Timer I/O Control Register (TIOR) ..................................................................... 106 8.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 114 8.2.5 Timer Status Register (TSR) ................................................................................ 116 8.2.6 Timer Counters (TCNT)....................................................................................... 118 8.2.7 Timer General Register (TGR) ............................................................................ 119 8.2.8 Timer Start Register (TSTR)................................................................................ 119 8.2.9 Timer Synchro Register (TSYR).......................................................................... 120 Bus Master Interface.......................................................................................................... 121 8.3.1 16-Bit Registers.................................................................................................... 121 8.3.2 8-Bit Registers...................................................................................................... 121
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8.2
8.3
8.4
8.5
8.6
8.7 8.8
Operation ........................................................................................................................... 123 8.4.1 Overview .............................................................................................................. 123 8.4.2 Basic Functions .................................................................................................... 123 8.4.3 Synchronous Operation ........................................................................................ 129 8.4.4 Buffer Operation .................................................................................................. 131 8.4.5 Cascade Connection Mode ................................................................................... 134 8.4.6 PWM Mode .......................................................................................................... 135 Interrupts............................................................................................................................ 140 8.5.1 Interrupt Sources and Priority Ranking................................................................ 140 8.5.2 A/D Converter Activation .................................................................................... 141 Operation Timing .............................................................................................................. 142 8.6.1 Input/Output Timing ............................................................................................ 142 8.6.2 Interrupt Signal Timing........................................................................................ 146 Notes and Precautions........................................................................................................ 148 MTU Output Pin Initialization .......................................................................................... 157 8.8.1 Operating Modes .................................................................................................. 157 8.8.2 Reset Start Operation............................................................................................ 158 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc................. 158 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc. ......................................................................................... 159
Section 9 8-Bit Timer 2 (TIM2) ...................................................................................... 169
9.1 Overview............................................................................................................................ 169 9.1.1 Features ................................................................................................................ 169 9.1.2 Block Diagram...................................................................................................... 170 9.1.3 Register Configuration ......................................................................................... 170 Register Descriptions......................................................................................................... 171 9.2.1 Timer 2 Control/Status Register (T2CSR) ........................................................... 171 9.2.2 Timer 2 Counter (T2CNT) ................................................................................... 172 9.2.3 Timer 2 Constant Register (T2COR) ................................................................... 173 Operation ........................................................................................................................... 174 9.3.1 Cyclic Count Operation........................................................................................ 174 9.3.2 T2CNT Count Timing.......................................................................................... 174 Interrupts............................................................................................................................ 175 9.4.1 Interrupt Source.................................................................................................... 175 9.4.2 Timing of Compare Match Flag Setting .............................................................. 175 9.4.3 Timing of Compare Match Flag Clearing ............................................................ 176
9.2
9.3
9.4
Section 10 Compare Match Timer (CMT) ................................................................... 177
10.1 Overview............................................................................................................................ 177 10.1.1 Features ................................................................................................................ 177 10.1.2 Block Diagram...................................................................................................... 178 10.1.3 Register Configuration ......................................................................................... 179
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10.2 Register Descriptions......................................................................................................... 180 10.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 180 10.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 181 10.2.3 Compare Match Timer Counter (CMCNT).......................................................... 182 10.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 183 10.3 Operation ........................................................................................................................... 183 10.3.1 Period Count Operation........................................................................................ 183 10.3.2 CMCNT Count Timing ........................................................................................ 184 10.4 Interrupts............................................................................................................................ 184 10.4.1 Interrupt Sources .................................................................................................. 184 10.4.2 Compare Match Flag Set Timing ......................................................................... 184 10.4.3 Compare Match Flag Clear Timing...................................................................... 185 10.5 Notes on Use...................................................................................................................... 186 10.5.1 Contention between CMCNT Write and Compare Match ................................... 186 10.5.2 Contention between CMCNT Word Write and Incrementation .......................... 187 10.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 188
Section 11 Watchdog Timer (WDT).............................................................................. 189
11.1 Overview............................................................................................................................ 189 11.1.1 Features ................................................................................................................ 189 11.1.2 Block Diagram...................................................................................................... 190 11.1.3 Register Configuration ......................................................................................... 191 11.2 Register Descriptions......................................................................................................... 191 11.2.1 Timer Counter (TCNT) ........................................................................................ 191 11.2.2 Timer Control/Status Register (TCSR) ................................................................ 192 11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 193 11.2.4 Register Access .................................................................................................... 194 11.3 Operation ........................................................................................................................... 195 11.3.1 Watchdog Timer Mode ........................................................................................ 195 11.3.2 Interval Timer Mode ............................................................................................ 197 11.3.3 Clearing the Standby Mode.................................................................................. 197 11.3.4 Timing of Setting the Overflow Flag (OVF)........................................................ 198 11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 198 11.4 Notes on Use...................................................................................................................... 199 11.4.1 TCNT Write and Increment Contention............................................................... 199 11.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 199 11.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 199 11.4.4 Internal Reset With the Watchdog Timer ............................................................ 199
Section 12 Serial Communication Interface (SCI1) .................................................. 201 12.1 Overview............................................................................................................................ 201 12.1.1 Features ................................................................................................................ 201 12.1.2 Block Diagram...................................................................................................... 202
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12.2
12.3
12.4 12.5
12.1.3 Pin Configuration ................................................................................................. 202 12.1.4 Register Configuration ......................................................................................... 203 Register Descriptions......................................................................................................... 203 12.2.1 Receive Shift Register (RSR1)............................................................................. 203 12.2.2 Receive Data Register (RDR1) ............................................................................ 203 12.2.3 Transmit Shift Register (TSR1)............................................................................ 204 12.2.4 Transmit Data Register (TDR1) .......................................................................... 204 12.2.5 Serial Mode Register (SMR1).............................................................................. 204 12.2.6 Serial Control Register (SCR1)............................................................................ 207 12.2.7 Serial Status Register (SSR1)............................................................................... 210 12.2.8 Bit Rate Register (BRR1)..................................................................................... 214 Operation ........................................................................................................................... 225 12.3.1 Overview .............................................................................................................. 225 12.3.2 Operation in Asynchronous Mode........................................................................ 227 12.3.3 Multiprocessor Communication ........................................................................... 237 12.3.4 Clock Synchronous Operation.............................................................................. 245 Interrupt ............................................................................................................................. 255 Notes on Use...................................................................................................................... 256
Section 13 A/D Converter (A/D)..................................................................................... 259
13.1 Overview............................................................................................................................ 259 13.1.1 Features ................................................................................................................ 259 13.1.2 Block Diagram...................................................................................................... 260 13.1.3 Pin Configuration ................................................................................................. 261 13.1.4 Register Configuration ......................................................................................... 262 13.2 Register Descriptions......................................................................................................... 262 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 262 13.2.2 A/D Control/Status Register (ADCSR)................................................................ 263 13.2.3 A/D Control Register (ADCR)............................................................................. 265 13.3 CPU Interface .................................................................................................................... 266 13.4 Operation ........................................................................................................................... 268 13.4.1 Single Mode (SCAN = 0) ..................................................................................... 268 13.4.2 Scan Mode (SCAN = 1) ....................................................................................... 270 13.4.3 Input Sampling and A/D Conversion Time.......................................................... 272 13.4.4 MTU Trigger Input Timing.................................................................................. 274 13.5 A/D Conversion Precision Definitions.............................................................................. 274 13.6 Notes on Use...................................................................................................................... 276 13.6.1 Analog Voltage Settings....................................................................................... 276 13.6.2 Handling of Analog Input Pins............................................................................. 276
Section 14 Pin Function Controller (PFC).................................................................... 279 14.1 Overview............................................................................................................................ 279 14.2 Register Configuration ...................................................................................................... 282
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14.3 Register Descriptions......................................................................................................... 283 14.3.1 Port A IO Register L (PAIORL) .......................................................................... 283 14.3.2 Port A Control Registers L1 and L2 (PACRL1, PACRL2) ................................. 283 14.3.3 Port B IO Register (PBIOR)................................................................................. 288 14.3.4 Port B Control Registers 1 and 2 (PVCR1, PBCR2)............................................ 288 14.3.5 Port C IO Register (PCIOR)................................................................................. 291 14.3.6 Port C Control Register (PCCR) .......................................................................... 292 14.3.7 Port D IO Register L (PDIORL) .......................................................................... 295 14.3.8 Port D Control Register L (PDCRL).................................................................... 296 14.3.9 Port E IO Register (PEIOR) ................................................................................. 298 14.3.10 Port E Control Register 2 (PECR2)...................................................................... 299
Section 15 I/O Ports (I/O).................................................................................................. 301 15.1 Overview............................................................................................................................ 301 15.2 Port A................................................................................................................................. 301 15.2.1 Register Configuration ......................................................................................... 302 15.2.2 Port A Data Register L (PADRL) ........................................................................ 303 15.3 Port B ................................................................................................................................. 304 15.3.1 Register Configuration ......................................................................................... 304 15.3.2 Port B Data Register (PBDR)............................................................................... 305 15.4 Port C ................................................................................................................................. 306 15.4.1 Register Configuration ......................................................................................... 306 15.4.2 Port C Data Register (PCDR)............................................................................... 307 15.5 Port D................................................................................................................................. 308 15.5.1 Register Configuration ......................................................................................... 308 15.5.2 Port D Data Register L (PDDRL) ........................................................................ 309 15.6 Port E ................................................................................................................................. 310 15.6.1 Register Configuration ......................................................................................... 310 15.6.2 Port E Data Register (PEDR) ............................................................................... 311 15.7 Port F ................................................................................................................................. 312 15.7.1 Register Configuration ......................................................................................... 312 15.7.2 Port E Data Register (PFDR) ............................................................................... 313 Section 16 160 kB Flash Memory (F-ZTAT).............................................................. 315
16.1 Features.............................................................................................................................. 315 16.2 Overview............................................................................................................................ 316 16.2.1 Block Diagram...................................................................................................... 316 16.2.2 Mode Transitions.................................................................................................. 317 16.2.3 On-Board Programming Modes ........................................................................... 318 16.2.4 Flash Memory Emulation in RAM....................................................................... 320 16.2.5 Differences between Boot Mode and User Program Mode ................................. 321 16.2.6 Block Configuration ............................................................................................. 322 16.3 Pin Configuration .............................................................................................................. 322
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16.4 Register Configuration ...................................................................................................... 323 16.5 Register Descriptions......................................................................................................... 324 16.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 324 16.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 327 16.5.3 Erase Block Register 1 (EBR1)............................................................................ 328 16.5.4 Erase Block Register 2 (EBR2)............................................................................ 328 16.5.5 RAM Emulation Register (RAMER) ................................................................... 329 16.6 On-Board Programming Modes ........................................................................................ 330 16.6.1 Boot Mode............................................................................................................ 331 16.6.2 User Program Mode ............................................................................................. 335 16.7 Programming/Erasing Flash Memory................................................................................ 336 16.7.1 Program Mode...................................................................................................... 336 16.7.2 Program-Verify Mode .......................................................................................... 337 16.7.3 Erase Mode........................................................................................................... 345 16.7.4 Erase-Verify Mode ............................................................................................... 346 16.7.5 Wait Time Widths in Programming/Erasing........................................................ 352 16.8 Protection........................................................................................................................... 353 16.8.1 Hardware Protection............................................................................................. 353 16.8.2 Software Protection .............................................................................................. 354 16.8.3 Error Protection .................................................................................................... 355 16.9 Flash Memory Emulation in RAM.................................................................................... 357 16.10 Note on Flash Memory Programming/Erasing .................................................................. 359 16.11 Flash Memory Programmer Mode ..................................................................................... 359 16.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 360 16.11.2 Programmer Mode Operation............................................................................... 362 16.11.3 Memory Read Mode............................................................................................. 363 16.11.4 Auto-Program Mode ............................................................................................ 366 16.11.5 Auto-Erase Mode.................................................................................................. 368 16.11.6 Status Read Mode................................................................................................. 370 16.11.7 Status Polling........................................................................................................ 371 16.11.8 Programmer Mode Transition Time..................................................................... 371 16.11.9 Notes On Memory Programming ......................................................................... 372
Section 17 RAM ................................................................................................................... 373
17.1 Overview............................................................................................................................ 373
Section 18 Power-Down State.......................................................................................... 375 18.1 Overview............................................................................................................................ 375 18.1.1 Power-Down States .............................................................................................. 375 18.1.2 Related Register.................................................................................................... 376 18.2 Standby Control Register (SBYCR).................................................................................. 377 18.3 Sleep Mode........................................................................................................................ 377 18.3.1 Transition to Sleep Mode ..................................................................................... 377
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18.3.2 Canceling Sleep Mode.......................................................................................... 378 18.4 Standby Mode.................................................................................................................... 378 18.4.1 Transition to Standby Mode ................................................................................. 378 18.4.2 Canceling the Standby Mode................................................................................ 380 18.4.3 Standby Mode Application Example.................................................................... 381
Section 19 Electrical Characteristics.............................................................................. 383 19.1 Absolute Maximum Ratings.............................................................................................. 383 19.2 DC Characteristics ............................................................................................................. 384 19.3 AC Characteristics ............................................................................................................. 387 19.3.1 Clock Timing........................................................................................................ 387 19.3.2 Control Signal Timing.......................................................................................... 389 19.3.3 Bus Timing ........................................................................................................... 391 19.3.4 Multifunction Timer Pulse Unit Timing .............................................................. 396 19.3.5 I/O Port Timing .................................................................................................... 397 19.3.6 Serial Communication Interface Timing.............................................................. 398 19.3.7 A/D Converter Timing ......................................................................................... 399 19.3.8 Test Conditions for AC Characteristics................................................................ 401 19.4 A/D Converter Characteristics .......................................................................................... 402 Appendix A On-Chip Peripheral Module Registers.................................................. 405 Appendix B Pin States........................................................................................................ 410
B.1 B.2 Pin States ........................................................................................................................... 410 Bus-Related Signals and Pin States ................................................................................... 411
Appendix C Product Lineup ............................................................................................. 412 Appendix D Package Dimensions................................................................................... 413
ix
x
Section 1 SH7018 Overview
1.1 SH7018 Features
The SH7018 is a CMOS single-chip microcomputer with a CPU based on Hitachi-original RISCtype SuperHTM* architecture as its core. It also provides peripheral functions essential to system configuration. The CPU incorporated into the chip supports the RISC (reduced instruction set computer) instruction set. Basic instructions execute in one cycle, so instruction execution times are extremely fast. The chip has an internal 32-bit architecture for efficient data processing. The CPU is capable of supporting applications employing real-time control. Such applications were not practical using previous microcomputers due to the extremely fast processing speeds required. It makes possible the development of systems providing high performance and excellent functionality at low cost. The chip incorporates several peripheral functions essential to system configuration, such as ROM, RAM, timers, serial communication interface (SCI), A/D converter, interrupt controller (INTC), and I/O ports. It also supports external memory access, which allows for efficient connections to external memory and LSI devices. These features help to reduce system costs substantially. The SH7018 employs on-chip flash memory with F-ZTATTM* (flexible zero turnaround time). In addition to allowing programming of the chip by writing to it using a program writer for LSI devices, software can be written to the flash memory and erased as necessary. This allows the firmware to be overwritten at the user site while the chip is mounted on the circuit board. Note: * SuperHTM and F-ZTATTM are trademarks of Hitachi, Ltd.
1
Table 1.1
Item CPU
Features
Specification * * * Original Hitachi architecture Internal 32-bit configuration General register machine General registers: 32-bit x 16 Control registers: 32-bit x 3 System registers: 32-bit x 4 * RISC (reduced instruction set computer) instruction set Instruction length: 16-bit fixed for efficient coding Load-store architecture (basic operations executed between registers) Extended branching instructions to minimize pipeline disturbance when branching Instruction set based on C language * * * Instruction execution time of one cycle per instruction (50 ns per instruction when operating at 20 MHz) Maximum address space of 4 GB supported by architecture On-chip multiplier The on-chip multiplier handles 32 x 32 64 multiplication operations in two to four cycles and 32 x 32 + 64 64 multiplication/accumulation operations in two to four cycles. * Pipeline 5-stage pipeline
Interrupt controller (INTC) * * Bus state controller (BSC) * *
Seven external interrupt pins (NMI, IRQ0 to IRQ3, IRQ6, IRQ7) 16-level priority setting supported Bus access to external memory and external devices supported 8-bit fixed external data bus Address space divided into four areas (SRAM space x 4 areas) Wait cycles may be specified (0 to 3 cycles) separately for each area.
* *
Chip select signals corresponding to memory areas are output. Wait cycles may be inserted using external WAIT signal.
2
Table 1.1
Item
Features (cont)
Specification * * * * * * 16-bit free running counter x 3 channels Eight compare match registers Interrupt requests are generated by compare match and overflow operations. 16-bit free running counter x 2 channels Compare registers: 1 per channel Interrupt requests are generated by compare match operations. Can be switched between watchdog timer and interval timer functions. Internal reset or interrupt generated by counter overflow. By specifying the power supply for the input/output circuitry, PV CC, the input/output voltage level for the following pins can be set to either 3.3 V or 5 V: RES, NMI, IRQ0, WAIT, D0 to D7, SCK, TxD, RxD, TIOC0A, TIOC0C (total 17 pins). 8-bit interval timer function Interrupt generated by compare match operations. Asynchronous or clock-synchronous mode is selectable (full duplex) On-chip dedicated baud rate generator Multi-processor communication function 62 inputs and outputs 8 inputs 10 bits x 8 channels Built-in sample and hold function RAM: 4 kB ROM: 160 kB (F-ZTAT)
Multifunction timer pulse unit (MTU) x 3 channels
Compare match timer (CMT) x 2 channels
Watchdog timer (WDT)
* *
5 V I/O pins
*
8-bit timer (TIM2)
* *
Serial communication interface (SCI)
* * *
I/O ports
* * * *
A/D converter
On-chip memory
* *
3
Table 1.1
Item
Features (cont)
Specification * Processing modes Program execution mode Exception processing mode * Operating modes Extended ROM enabled mode Boot mode User program mode Program mode * Low-power-consumption modes Sleep mode Standby mode
Operating modes
Clock pulse generator (CPG) Product lineup
On-chip clock pulse generator (1 : 1 oscillation using duty correction circuit) Product Name SH7018 Voltage 3.3 V Operating Frequency 20 MHz Product Code HD64F7018X20 Package TFP-100B
4
1.2
Block Diagram
PB8/IRQ6/A20/WAIT
PA12/WRL
NMI RES MD0 (Vss) MD1 (Vcc) MD2 (Vss) MD3 (Vss) EXTAL XTAL FWP* Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc PVcc AVcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss AVss
Note: * FWE during write mode
;; ;;;;; ;;; ;;;;; ; ;; ; ;; ;; ;;;;; ;; ;; ;;;;; ; ;; ;;
PA11/CS1 PA10/CS0 PA9/IRQ3 PA8/IRQ2 PA2/IRQ0 PA5/SCK PA7/CS3 PA6/CS2 PA3/RxD PA4/TxD PB3/IRQ1 PB7/A19 PB6/A18 PB1/A17 PA1 PA0 PB0/A16 PB5 PB4 PB2 Port A Port B
RAM 4kB
PA14/RD
PA15/CK
PB9/IRQ7/A21
PC15/A15 PC14/A14 PC13/A13 PC12/A12 PC11/A11 PC10/A10 PC9/A9 PC8/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0
CPU
Flash ROM 160 kB
Interrupt controller
Bus state controller
Timers
Serial communication interface (x 1 channel)
Port C
PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0
Multifunction timer pulse unit
x3 x2 x1
A/D converter
Watchdog timer
Port F
Port E
Figure 1.1 Block Diagram of SH7018 (TFP-100B Pins)
;
PE2/TIOC0C PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE0/TIOC0A
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
PE14
PE13
PE12
PE11
PE10
PE9
PE8
: Peripheral address bus : Peripheral data bus : On-chip address bus : On-chip upper data : On-chip lower data
Port D
Compare match 8-bit timer
5
1.3
1.3.1
Pin Description
Pin Layout
PE2/TIOC0C PE0/TIOC0A
PA15/CK
PD0/D0
PD1/D1
PD2/D2
PD3/D3
PD4/D4
PD5/D5
PD6/D6
PD7/D7
EXTAL
FWP*
XTAL
PVcc
MD0
MD1
MD2
MD3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
Vss PE4/TIOC1A PE5/TIOC1B Vcc PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14 Vss PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVcc Vcc
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9
51
RES
NMI
Vcc
Vcc
Vss
Vss
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
PA2/IRQ0 PA3/RxD PA4/TxD PA5/SCK PB8/IRQ6/A20/WAIT Vcc PA8/IRQ2 Vss PA9/IRQ3 PA0 PA1 Vcc PA6/CS2 PA7/CS3 PA10/CS0 PA11/CS1 PA12/WRL PA14/RD Vss PB9/IRQ7/A21 Vcc PB7/A19 PB6/A18 PB5 PB4
TOP VIEW (TFP-100B)
PC10/A10
PC11/A11
PC12/A12
PC13/A13
PC14/A14
PC15/A15
PB3/IRQ1
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PC8/A8
PC9/A9
PB0/A16
PB1/A17
Vcc
PB2
Vss
Vss
Vss
INDEX
Vss
5 V pins Note: * FWE during write mode
Figure 1.2 SH7018 Pin Layout (TFP-100B: Top View)
6
1.3.2
Pin Functions
The pin functions are listed in table 1.2. Table 1.2
Type Power supply
Pin Functions
Abbreviation VCC I/O Input Name Power supply Function Connect the power supply for the entire system to the VCC pin. The chip will not function if this pin is left open. Connect this pin to a ground. Connect the ground for the entire system to the VSS pin. The chip will not function if this pin is left open.
VSS
Input
Ground
PVcc Clock EXTAL
Input Input
Power supply for This pin is the power supply for input/output circuit an input/output circuit. External clock Connect this pin to a crystal oscillator. Alternately, the EXTAL pin may be used for external clock input. Connect this pin to a crystal oscillator. Supplies the system clock signal to peripheral devices. Applying a low-level signal to this pin triggers a power-on reset. This pin determines the operating mode. Do not change the input level while the system is operating. This pin is used to prevent programming or erasing of the flash memory. This is a non-maskable interrupt request pin. The user can select whether requests are accepted at the rising or the falling edge. These are maskable interrupt request pins. Level input and edge input selection are supported. 7
XTAL CK System control RES
Input Output Input
Crystal System clock Power-on reset
Operating mode control
MD0 to MD3
Input
Mode setting
FWP
Input
Flash memory write prevent Non-maskable interrupt
Interrupts
NMI
Input
IRQ0 to IRQ3, Input IRQ6, IRQ7
Interrupt request 0 to 3, 6, and 7
Table 1.2
Type Address bus Data bus Bus control
Pin Functions (cont)
Abbreviation A0 to A21 D0 to D7 CS0 to CS3 I/O Output Input/ output Output Name Address bus Data bus Chip select 0 to 3 Function These pins are used for address output. This is an 8-bit bi-directional data bus. These pins are used for chip select signals for external memory or devices. Indicates that data is being read from an external device. Indicates that the lower eight external data bits (bits 7 to 0) are being written to. This input is used to insert a wait cycle when accessing the external area. Channel 0 input capture input/output compare output/PWM output pin. Channel 1 input capture input/output compare output/PWM output pin. Channel 2 input capture input/output compare output/PWM output pin. Transmit data output pin.
RD WRL
Output Output
Read Write
WAIT
Input
Wait
Multifunction timer TIOC0A pulse unit (MTU) TIOC0C
Input/ output
MTU input capture/output compare (channel 0) MTU input capture/output compare (channel 1) MTU input capture/output compare (channel 2) Transmit data
TIOC1A TIOC1B
Input/ output
TIOC2A TIOC2B
Input/ output
Serial communication interface (SCI)
TxD
Output
RxD SCK
Input Input/ output
Receive data Serial clock
Receive data input pin. Clock input/output pin.
8
Table 1.2
Type
Pin Functions (cont)
Abbreviation AVCC AVSS AN0 to AN7 I/O Input Input Input Input/ output Input/ output Input/ output Input/ output Name Analog power supply Analog ground Analog inputs General port General port General port General port General port General port Function Connect to VCC potential when using an analog power supply. Connect to Vss potential when using an analog power supply. Analog signal input terminals. General I/O port pins. I/O can be specified one bit at a time. General I/O port pins. I/O can be specified one bit at a time. General I/O port pins. I/O can be specified one bit at a time. General I/O port pins. I/O can be specified one bit at a time. General I/O port pins. I/O can be specified one bit at a time. General I/O port pins.
A/D converter
I/O ports
PA15, 14, 12 to 0 PB9 to 0 PC15 to 0 PD7 to 0
PE14 to 4, 2, 0 Input/ output PF7 to 0 Input
Note: The following power-on/power-off order is recommended. 1. Powering on (1) Turn on the 5 V power (PVCC) first, then the 3 V power (VCC, PLLVCC, AVCC). (2) Pin states are undefined while only 5 V power is on, as reset input is invalid. 2. Powering off (1) Power off in the reverse order to powering on: turn off the 3 V power first, then the 5 V power. (2) Pin states are undefined while only 5 V power is being supplied. 3. Power-on/off interval To minimize the length of time during which pin states are undefined, the power-on/off interval should be kept as short as possible. Also, the system design should ensure that erroneous system operation will not result from pin states becoming undefined.
9
10
Section 2 CPU
2.1 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn)
The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers.
31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. 0
2.
Figure 2.1 General Registers
11
2.1.2
Control Registers
The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows a control register.
31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. This bit always read 0. The write value should always be 0. Bits I0 to I3: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. This bit always read 0. The write value should always be 0. 31 GBR 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area.
31
Figure 2.2 Control Registers
12
2.1.3
System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows a system register.
31 MACH MACL 0
Multiply and accumulate (MAC) registers high and low (MACH, MACL): Stores the results of multiply and accumulate operations. Procedure register (PR): Stores a return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction.
31 PR
0
31 PC
0
Figure 2.3 System Registers 2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers
Register R0 to R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I3 to I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table
Classification General registers
13
2.2
2.2.1
Data Formats
Data Format in Registers
Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4).
31 Longword 0
Figure 2.4 Longword Operand 2.2.2 Data Format in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.5).
Address m + 1 Address m 31 Byte Address 2n Address 4n 23 Byte Word Longword 15 Byte Address m + 3 7 Byte Word 0
Address m + 2
Figure 2.5 Byte, Word, and Longword Alignment 2.2.3 Immediate Data Format
Byte (8-bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register.
14
Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement.
2.3
2.3.1
Instruction Features
RISC-Type Instruction Set
All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 35 ns at 28.7 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data (table 2.2). Table 2.2 Sign Extension of Word Data
Description Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. Example of Conventional CPU ADD.W #H'1234,R0
SH7018 CPU MOV.W ADD @(disp,PC),R1 R1,R0 ......... .DATA.W H'1234
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions.
15
Table 2.3
Delayed Branch Instructions
Description Executes an ADD before branching to TRGET Example of Conventional CPU ADD.W BRA R1,R0 TRGET
SH7018 CPU BRA ADD TRGET R1,R0
Multiplication/Accumulation Operation: 16-bit x 16-bit 32-bit multiplication operations are executed in one to two cycles. 16-bit x 16-bit + 64-bit 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit x 32-bit 64-bit and 32-bit x 32-bit + 64bit 64-bit multiplication/accumulation operations are executed in two to four cycles. T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed (table 2.4). Table 2.4 T Bit
Description T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. Example of Conventional CPU CMP.W BGE BLT R1,R0 TRGET0 TRGET1 #1,R0 TRGET
SH7018 CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET
T bit is not changed by ADD. T bit is SUB.W set when R0 = 0. The program BEQ branches if R0 = 0.
Immediate Data: Byte (8-bit) immediate data resides in instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5).
16
Table 2.5
Immediate Data Accessing
SH7018 CPU MOV MOV.W #H'12,R0 @(disp,PC),R0 ................. .DATA.W H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 MOV.L #H'12345678,R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0
Classification 8-bit immediate 16-bit immediate
32-bit immediate
MOV.L
Note: @(disp, PC) accesses the immediate data.
Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing
SH7018 CPU MOV.L MOV.B @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0
Classification Absolute address
16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing
SH7018 CPU MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2
Classification 16-bit displacement
17
2.3.2
Addressing Modes
Table 2.8 describes addressing modes and effective address calculation. Table 2.8
Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing
Addressing Modes and Effective Addresses
Instruction Format Effective Addresses Calculation Rn @Rn The effective address is register Rn. (The operand is the contents of register Rn.) The effective address is the content of register Rn. Rn @Rn+ Rn Rn (After the instruction executes) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) Equation -- Rn
The effective address is the content of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn
Pre-decrement indirect register addressing
@-Rn
The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4
18
Table 2.8
Addressing Mode
Addressing Modes and Effective Addresses (cont)
Instruction Format Effective Addresses Calculation @(disp:4, The effective address is Rn plus a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Equation Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4
Indirect register addressing with displacement
Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register Rn addressing + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the GBR value plus an GBR) 8-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Rn + R0
Rn + R0
Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4
19
Table 2.8
Addressing Mode
Addressing Modes and Effective Addresses (cont)
Instruction Format Effective Addresses Calculation Equation GBR + R0
Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR addressing GBR + R0 PC relative addressing with displacement @(disp:8, The effective address is the PC value plus an 8-bit PC) displacement (disp). The value of disp is zeroextended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) x 2/4 (for longword) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 GBR + R0
Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4
+
20
Table 2.8
Addressing Mode PC relative addressing
Addressing Modes and Effective Addresses (cont)
Instruction Format Effective Addresses Calculation disp:8 The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) x 2 disp:12 The effective address is the PC value sign-extended with a 12-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) x 2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + Rn PC + Rn + PC + disp x 2 PC + disp x 2 + PC + disp x 2 Equation PC + disp x 2
Immediate addressing
#imm:8 #imm:8 #imm:8
The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled.
-- -- --
21
2.3.3
Instruction Format
Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: * * * * * xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement
Table 2.9
Instruction Formats
Source Operand -- 0 xxxx xxxx xxxx -- nnnn: Direct register nnnn: Direct register MOVT Rn Destination Operand -- Example NOP
Instruction Formats 0 format 15 xxxx n format
15 xxxx nnnn xxxx xxxx
0
Control register or system register Control register or system register
STS
MACH,Rn
nnnn: Indirect pre- STC.L decrement register Control register or system register Control register or system register -- -- LDC LDC.L
SR,@-Rn
m format 15 xxxx mmmm xxxx xxxx 0
mmmm: Direct register mmmm: Indirect post-increment register mmmm: Direct register mmmm: PC relative using Rm
Rm,SR @Rm+,SR
JMP BRAF
@Rm Rm
22
Table 2.9
Instruction Formats (cont)
Source Operand mmmm: Direct register 0 nnnn mmmm xxxx mmmm: Direct register mmmm: Indirect post-increment register (multiply/ accumulate) nnnn*: Indirect post-increment register (multiply/ accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn Destination Operand nnnn: Direct register nnnn: Indirect register MACH, MACL Example ADD MOV.L Rm,Rn Rm,@Rn
Instruction Formats nm format 15 xxxx
MAC.W @Rm+,@Rn+
MOV.L
Rm,@-Rn
MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0
md format 15 xxxx nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx nnnn mmmm dddd 0 0 xxxx mmmm dddd 0
mmmmdddd: indirect register with displacement R0 (Direct register)
nnnndddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register
MOV.B R0,@(disp,Rn)
mmmm: Direct register
MOV.L Rm,@(disp,Rn)
mmmmdddd: Indirect register with displacement
MOV.L @(disp,Rm),Rn
Note: * In multiply/accumulate instructions, nnnn is the source register.
23
Table 2.9
Instruction Formats (cont)
Source Operand 0 dddddddd: Indirect GBR with displacement R0(Direct register) dddddddd: PC relative with displacement dddddddd: PC relative Destination Operand Example
Instruction Formats d format 15 xxxx xxxx dddd dddd
R0 (Direct register) MOV.L @(disp,GBR),R0
dddddddd: Indirect GBR with displacement
MOV.L R0,@(disp,GBR)
R0 (Direct register) MOVA @(disp,PC),R0 -- -- BF BRA label label
d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx i format 15 xxxx xxxx iiii iiii 0 nnnn dddd dddd 0 0
dddddddddddd: PC relative
(label = disp + PC) nnnn: Direct register MOV.L @(disp,PC),Rn
dddddddd: PC relative with displacement iiiiiiii: Immediate iiiiiiii: Immediate
Indirect indexed GBR
AND.B #imm,@(R0,GBR) #imm,R0
R0 (Direct register) AND
iiiiiiii: Immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate
-- nnnn: Direct register
TRAPA ADD
#imm #imm,Rn
24
2.4
Instruction Set by Classification
Table 2.10 Classification of Instructions
Operation Classification Types Code Function Data transfer 5 MOV No. of Instructions
Data transfer, immediate data transfer, 39 peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check 33
MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV
CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow
25
Table 2.10 Classification of Instructions (cont)
Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 11 14 No. of Instructions 14
26
Table 2.10 Classification of Instructions (cont)
Operation Classification Types Code Function System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Shift into power-down mode Storing control register data Storing system register data Trap exception processing 142 No. of Instructions 31
Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification.
27
Table 2.11 Instruction Code Format
Item Instruction Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* 1 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 . . . 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted* 2 Value of T bit after instruction is executed. An em-dash (--) in the column means no change.
Instruction code
MSB LSB
Operation
, (xx) M/Q/T & | ^ ~ <>n
Execution cycles T bit
-- --
Notes: 1. Depending on the operand size, displacement is scaled x1, x2, or x4. For details, see the SH-1/SH-2/SH-DSP Programming Manual. 2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
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Table 2.12 Data Transfer Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV #imm,Rn
Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100
Operation #imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn,Rm + 1 Rm (Rm) Sign extension Rn,Rm + 2 Rm (Rm) Rn,Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn)
MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn
MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn)
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Table 2.12 Data Transfer Instructions (cont)
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0 Rn
Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
Operation Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) Sign extension R0 (disp x 2 + GBR) Sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC R0 T Rn
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
Rm Swap the bottom two 1 bytes Rn Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn 1 1
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Table 2.13 Arithmetic Operation Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1
Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn
Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100
Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T If Rn Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn > 0, 1 T If Rn 0, 1 T If Rn and Rm have an equivalent byte, 1T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T
T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0
CMP/STR Rm,Rn
DIV1 DIV0S DIV0U
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001
1 1 1
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Table 2.13 Arithmetic Operation Instructions (cont)
Execution Cycles 2 to 4*
Instruction DMULS.L Rm,Rn
Instruction Code 0011nnnnmmmm1101
Operation Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bit Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bit
T Bit --
DMULU.L Rm,Rn
0011nnnnmmmm0101
2 to 4*
--
DT
Rn
0100nnnn00010000
Rn - 1 Rn, when Rn 1 is 0, 1 T. When Rn is nonzero, 0 T A byte in Rm is signextended Rn A word in Rm is signextended Rn A byte in Rm is zeroextended Rn A word in Rm is zeroextended Rn Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 64 bit Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bit Rn x Rm MACL, 32 x 32 32 bit Signed operation of Rn x Rm MAC 16 x 16 32 bit Unsigned operation of Rn x Rm MAC 16 x 16 32 bit 0-Rm Rn 0-Rm-T Rn, Borrow T 1 1 1 1 3/(2 to 4)* 3/(2)*
Comparison result -- -- -- -- --
EXTS.B EXTS.W EXTU.B EXTU.W MAC.L
Rm,Rn Rm,Rn Rm,Rn Rm,Rn @Rm+,@Rn+
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
--
MUL.L MULS.W
Rm,Rn Rm,Rn
0000nnnnmmmm0111 0010nnnnmmmm1111
2 to 4* 1 to 3*
-- --
MULU.W
Rm,Rn
0010nnnnmmmm1110
1 to 3*
--
NEG NEGC
Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010
1 1
-- Borrow
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Table 2.13 Arithmetic Operation Instructions (cont)
Execution Cycles 1 1 1
Instruction SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn
Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
Operation Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T
T Bit -- Borrow Overflow
Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.)
Table 2.14 Logic Operation Instructions
Execution Cycles 1 1 3 1 1 1 3 4 1 1 3 1 1 3
Instruction AND AND Rm,Rn #imm,R0
Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR)
T Bit -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- --
AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
TAS.B @Rn TST TST Rm,Rn #imm,R0
TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0
XOR.B #imm,@(R0,GBR)
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Table 2.15 Shift Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn
Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
Operation T Rn MSB LSB Rn T T Rn T T Rn T T Rn 0 MSB Rn T T Rn 0 0 Rn T Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn
T Bit MSB LSB MSB LSB MSB LSB MSB LSB -- -- -- -- -- --
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Table 2.16 Branch Instructions
Instruction BF label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Exec. Cycles 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 T Bit -- -- -- -- -- -- -- -- -- -- --
BF/S label BT label
BT/S label BRA label
BRAF Rm BSR label
BSRF Rm JMP JSR RTS @Rm @Rm
Note: * One state when it does not branch.
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Table 2.17 System Control Instructions
Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Operation 0T 0 MACH, MACL Rm SR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm No operation Delayed branch, stack area PC/SR 1T Sleep SR Rn GBR Rn VBR Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, BR (Rn) MACH Rn MACL Rn PR Rn Exec. Cycles 1 1 1 1 1 3 3 3 1 1 1 T Bit 0 -- LSB -- -- LSB -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- --
LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR
LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS
(Rm) MACH, Rm + 4 Rm 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1
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Table 2.17 System Control Instructions (cont)
Instruction STS.L STS.L STS.L TRAPA MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC/SR stack area, (imm) PC Exec. Cycles 1 1 1 8 T Bit -- -- -- --
Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
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2.5
2.5.1
Processing States
State Transitions
The CPU has for processing states: reset, exception processing, program execution, and powerdown. Figure 2.6 shows the transitions between the states.
From all states when RES= 0
Power-on reset state
Reset state RES= 1 Interrupt triggered Exception processing state Exception processing triggered Exception processing ends NMI interrupt triggered
Program execution state Sleep instruction when SBY bit cleared Sleep instruction when SBY bit set
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions Between Processing States
Reset State: The CPU resets in this state. When the RES pin goes low, a power-on reset results. Exception Processing State: This is a transient state that occurs when the CPU's processing state flow is altered due to the triggering of exception processing. In the case of a reset, the execution start address and stack pointer (SP) initial value are fetched from the exception processing vector table as the initial values of the program counter (PC) and stored. The CPU then branches to the execution start address and execution of the program begins.
38
In the case of an interrupt or the like, the SP is accessed and the PC and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table. The CPU then branches to that address and execution of the program begins. The processing state which follows is the program execution state. Program Execution State: In this state the CPU executes programs sequentially. Power-Down State: In this state CPU operation halts in order to consume less power. The SLEEP instruction causes the CPU to enter the power-down state. This state has two modes, the sleep mode and the standby mode. 2.5.2 Power-Down State
The power-down state is one of the CPU's processing states. In this state CPU operation halts, in addition to the execution of programs, and power consumption is reduced. It has two modes, the sleep mode and the standby mode. Sleep Mode: Issuing the SLEEP instruction when the standby bit (SBY) of standby control register (SBYCR) is cleared to 0 causes the CPU to enter the sleep mode. In the sleep mode CPU operation is halted, but data stored in the CPU's internal registers and in on-chip RAM is retained. The functions of on-chip peripheral modules other than the CPU do not halt. A power-on reset or any interrupt causes the CPU to recover from the sleep mode. Exception processing then takes place, after which the CPU enters the normal program execution mode. Standby Mode: Issuing the SLEEP instruction when SBY of SBYCR is set to 1 causes the CPU to enter the standby mode. In the standby mode the functioning of the CPU, on-chip peripheral modules, and oscillator are halted. If the chip enters the standby mode while a multiplier instruction is executing, the MACH and MACL values become uncertain. A power-on reset or NMI interrupt causes the chip to recover from the sleep mode. After a reset the oscillator stabilization time elapses, after which exception processing takes place and then the chip enters the normal program execution mode. In the case of an NMI interrupt, the oscillator stabilization time must elapse, after which exception processing takes place and then the chip enters the normal program execution mode. This mode halts the operation of the oscillator, so power consumption is decreased substantially.
39
Table 2.18 Power-Down State
State Transition Conditions On-Chip Contents Contents Peripheral of CPU of On-Chip I/O Port Pin Modules Registers RAM States Retained Retained Retained Recovery Method (1) Interrupt (2) Power-on reset Retained Retained or Hi-Z (1) NMI interrupt (can be specified (2) Power-on reset by user)
Mode Sleep mode
Clock
CPU
SLEEP command Operating Halted Operating issued when SBY of SBYCR is cleared to 0 Halted
Standby SLEEP command mode issued when SBY of SBYCR is set to 1
Halted Halted or Retained initialized*
Note: * Differs depending on the peripheral module and pin.
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Section 3 Operating Modes
3.1 Operating Mode Selection
The SH7018 has four operating modes: MCU mode, boot mode, user program mode, and programmer mode. The settings of the mode pins (MD3 to MD0) determine the mode in which the chip operates. The mode pin settings must not be changed while the chip is operating (while power is being supplied). The method of selecting the operating mode is shown in table 3.1. Table 3.1 Operating Mode Selection
Pin Settings FWP 1 0 0 1 MD3* 1 MD2* 1 MD1 0 0 0 1 0 0 0 1 1 0 1 0 MD0 0 0 0 1 Operating Mode MCU mode Boot mode* 1 On-Chip ROM CS0 Bus Width Enabled Enabled 8 bits* 2 8 bits* 2 8 bits* 2 --
User program mode* 1 Enabled Programmer mode* 1 Enabled
Notes: 1. F-ZTAT version only. 2. Set using BCR1 of BSC.
3.2
Description of Operating Modes
MCU Mode: The on-chip ROM is enabled in the MCU mode. The bus width for the on-chip ROM space is 32 bits. Boot Mode: Refer to section 16.6.1 Boot Mode for information on the boot mode. User Program Mode: Refer to section 16.6.2 User Program Mode for information on the user program mode. Programmer Mode: Refer to section 16.11 Flash Memory Programmer Mode for information on the programmer mode.
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3.3
Pin Configuration
The functions of the pins relating to the operating modes are shown in table 3.2. Table 3.2
Pin Name XTAL EXTAL MD0 MD1 MD2 MD3
Pin Functions
I/O Input Input Input Input Input Input Function Connected to the crystal resonator. Connected to the crystal resonator, or used as input pin for external clock. The level at this pin is used in the operating mode specification. The level at this pin is used in the operating mode specification. The level at this pin is used in the operating mode specification. The level at this pin is used in the operating mode specification.
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Section 4 Clock Pulse Generator (CPG)
4.1 Overview
The clock pulse generator (CPG) supplies clock pulses within the SH7018 and to external devices. The SH7018's CPG operates the SH7018 at a frequency equal to the oscillation frequency of the crystal resonator. The CPG is composed of an oscillator and a duty adjustment circuit (figure 4.1). There are two ways of generating a clock with the CPG: by connecting a crystal resonator, or by inputting an external clock.
CPG
XTAL Oscillator EXTAL Duty adjustment circuit Internal clock ()
CK (system clock)
Figure 4.1 CPG Block Diagram
4.2
Clock Source
Either a crystal resonator or an external clock can be selected as the clock pulse source. 4.2.1 Crystal Resonator Connection
Circuit Configuration: Figure 4.2 shows the method of connecting a crystal resonator. Use the damping resistance (Rd) shown in table 4.1. An AT-cut parallel-resonance type crystal resonator with the same frequency as the system clock (CK) should be used. Load capacitors (CL1, C L2 ) must be connected as shown in the figure. The clock pulses generated by the crystal resonator and internal oscillator are sent to the duty adjustment circuit. After the duty has been adjusted, the pulses are supplied within the SH7018 chip and to external devices.
43
CL1 EXTAL CL2 XTAL Rd
CL1 = CL2 = 18 to 22
Figure 4.2 Example of Crystal Resonator Connection Table 4.1 Damping Resistance Value
20 0
Frequency (MHz) Rd ()
Crystal Resonator: Figure 4.3 shows an equivalent circuit for the crystal resonator. Use a crystal resonator with the characteristics shown in table 4.2.
L CL Rs
XTAL Co
EXTAL
Figure 4.3 Crystal Resonator Equivalent Circuit Table 4.2 Crystal Resonator Characteristics
Frequency (MHz) Parameter Rs max () Co max (pF) 20 60 7
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4.2.2
External Clock Input
Input the external clock to the EXTAL pin and leave the XTAL pin open (figure 4.4.). The external clock frequency should be the same as that of the system clock (CK).
XTAL
Open
EXTAL
External clock input
Figure 4.4 External Clock Input
4.3
Usage Notes
Note on Board Design: Place the crystal resonator and load capacitors as close as possible to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that other signal lines to not cross the EXTAL and XTAL pin signal lines.
Avoid crossing signal lines SH7018
CL1
XTAL
CL2
EXTAL
Figure 4.5 Note on Board Design
45
Notes on Duty Adjustment: Duty adjustment circuit is performed on an input clock of 5 MHz or higher. With a frequency of less than 5 MHz, duty adjustment may not be performed, but AC characteristics tCH (clock high-level width) and tCL (clock low-level width) are satisfied, and there is no problem with SH7018 internal operation. Figure 4.6 shows the basic characteristics of the duty adjustment circuit. The duty adjustment circuit does not correct for transient fluctuations or jitter in the input clock. Thus, several tens of s are required until duty adjustment is performed and a stable clock is obtained.
70 60 50 40
Input duty 70
Output duty (%)
60 50 40 30
30
1
2
5
10
20
Input frequency (MHz)
Figure 4.6 Duty Adjustment Circuit Characteristics
46
Section 5 Exception Processing
5.1
5.1.1
Overview
Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 5.1
Exception Reset Address error Interrupt
Types of Exception Processing and Priority Order
Source Power-on reset CPU address error NMI IRQ On-chip peripheral modules: * * * * * * Multifunction timer/pulse unit (MTU) Serial communications interface (SCI) A/D converter (A/D) Compare match timer (CMT) Watchdog timer (WDT) 8-bit timer 2 (TIM2) Priority High
Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay branch Low instruction* 1 or instructions that rewrite the PC* 2) Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF.
47
5.1.2
Exception Processing Operations
The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2
Exception
Timing of Exception Source Detection and the Start of Exception Processing
Source Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Trap instruction General illegal instructions Illegal slot instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC.
Power-on reset Address error Interrupts Instructions
When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses). See section 5.1.3, Exception Processing Vector Table, for more information. 0 is then written to the vector base register (VBR) and 1111 is written to the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3 to I0). For address error and instruction exception processing, the I3 to I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address.
48
5.1.3
Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table
Vector Numbers PC SP (Reserved by system) 0 1 2 3 General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) (Reserved by system) CPU address error (Reserved by system) Interrupts (Reserved by system) NMI 4 5 6 7 8 9 10 11 12 : 31 Trap instruction (user vector) 32 : 63 H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000F
Exception Sources Power-on reset
49
Table 5.3
Exception Processing Vector Table (cont)
Vector Numbers IRQ0 IRQ1 IRQ2 IRQ3 64 65 66 67 68 69 Vector Table Address Offset H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F H'00000120 to H'00000124 : H'000003FC to H'000003FF
Exception Sources Interrupts
(Reserved by system)
Interrupts
IRQ6 IRQ7
70 71 72 : 255
On-chip peripheral module*
Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors and Priorities.
Table 5.4
Calculating Exception Processing Vector Table Addresses
Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4
Exception Source Resets Address errors, interrupts, instructions
Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3.
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5.2
5.2.1
Resets
Reset
A reset has the highest priority of any exception source. As shown in table 5.5, a power-on reset initializes the internal state of the CPU and the on-chip peripheral module registers. Table 5.5 Types of Resets
Conditions for Transition to Reset Status Type Power-on reset RES Low CPU Initialized Internal Status On-Chip Peripheral Module Initialized
5.2.2
Power-On Reset
When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 t cyc (when the clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See Appendix B, Pin Status, for the status of individual pins during the power-on reset status. In the power-on reset status, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU will then operate as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the program counter (PC) and SP and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on.
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5.3
Address Errors
Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6
Bus Cycle Type Instruction fetch Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Data read/write Word data accessed from even address Word data accessed from odd address Longword data accessed from other than a longword boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* Note: * See section 7, Bus State Controller. Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) None (normal) Address error occurs
Bus Cycles and Address Errors
5.3.1
Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed branch.
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5.4
Interrupts
Table 5.7 shows the sources that start up interrupt exception processing. These are divided into NMI, IRQ and on-chip peripheral modules. Table 5.7
Type NMI IRQ On-chip peripheral module
Interrupt Sources
Request Source NMI pin (external input) IRQ0 to IRQ3, IRQ6, IRQ7 (external input) Multifunction timer/pulse unit (MTU) Serial communications interface (SCI) A/D converter Compare match timer (CMT) Watchdog Timer (WDT) 8-bit timer 2 (TIM2) Number of Sources 1 6 11 4 1 2 1 1
Each interrupt source is allocated a different vector number and vector table offset. See section 6, Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors and Priorities, for more information on vector numbers and vector table address offsets. 5.4.1 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt priority level is 15. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority level setting registers A through H (IPRA to IPRH) as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers A to H (IPRA to IPRH), for more information on IPRA to IPRH.
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Table 5.8
Type NMI IRQ
Interrupt Priority Order
Priority Level 16 0 to 15 0 to 15 Comment Fixed priority level. Cannot be masked. Set with interrupt priority level setting registers A through H (IPRA to IPRH). Set with interrupt priority level setting registers A through H (IPRA to IPRH).
On-chip peripheral module
5.4.2
Interrupt Exception Processing
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt exception processing.
5.5
Exceptions Triggered by Instructions
Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.9. Table 5.9
Type Trap instructions Illegal slot instructions
Types of Exceptions Triggered by Instructions
Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC Comment -- Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF --
General illegal instructions
Undefined code anywhere besides in a delay slot
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5.5.1
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 5.5.2 Illegal Slot Instructions
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. Illegal slot exception processing also starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 5.5.3 General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code.
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5.6
When Exception Sources Are Not Accepted
When an address error or interrupt is generated after a delayed branch instruction or interruptdisabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction
Exception Source Point of Occurrence Immediately after a delayed branch instruction*1 instruction*2 Address Error Not accepted Accepted Interrupt Not accepted Not accepted
Immediately after an interrupt-disabled
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
5.6.1
Immediately after a Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction located immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after an Interrupt-Disabled Instruction
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors are accepted.
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5.7
Stack Status after Exception Processing Ends
The status of the stack after exception processing ends is as shown in table 5.11. Table 5.11 Types of Stack Status After Exception Processing Ends
Types Address error Stack Status
SP
Address of instruction 32 bits after executed instruction SR 32 bits
Trap instruction
SP
Address of instruction after TRAPA instruction SR
32 bits 32 bits
General illegal instruction
SP
Start address of illegal instruction SR
32 bits 32 bits
Interrupt
SP
Address of instruction after executed instruction 32 bits SR 32 bits
Illegal slot instruction
SP
Jump destination address of delay branch instruction 32 bits SR 32 bits
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5.8
5.8.1
Notes on Use
Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing
When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. Address errors will then also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is -4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined.
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Section 6 Interrupt Controller (INTC)
6.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 Features
The INTC has the following features: * 16 levels of interrupt priority: By setting the eight interrupt-priority level registers, the priorities of IRQ interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. * NMI noise canceler function: NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler.
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6.1.2
Block Diagram
Figure 6.1 is a block diagram of the INTC.
NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7
Input control
CPU
Priority ranking judgment
Comparator
Interrupt request
SR I3 I2 I1 I0 MTU CMT SCI1 A/D WDT TIM2 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) CPU
ICR ISR
IPR
IPRA to IPRH Bus interface Internal bus
Module bus INTC MTU: CMT: SCI1: A/D: WDT: TIM2: Multifunction timer pulse unit Compare match timer Serial communication interface A/D converter Watchdog Timer 8-bit timer
ICR: Interrupt control register ISR: IRQ ststus register IPRA to IPRH: Interrupt priority level setting registers A to H SR: Status register
Figure 6.1 INTC Block Diagram
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6.1.3
Pin Configuration
Table 6.1 shows the INTC pin configuration. Table 6.1
Name Non-maskable interrupt input pin Interrupt request input pins
Pin Configuration
Abbreviation NMI IRQ0 to IRQ3, IRQ6, IRQ7 I/O I I Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals
6.1.4
Register Configuration
The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 6.2
Name Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt control register IRQ status register
Register Configuration
Abbr. IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH ICR ISR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2
Initial Value Address H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 *
1
Access Sizes 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
H'FFFF8348 H'FFFF834A H'FFFF834C H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A
R(W)* H'0000
Notes: 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags.
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6.2
Interrupt Sources
There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 6.2.1 NMI Interrupts
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. 6.2.2 IRQ Interrupts
IRQ interrupts are requested by input from pins IRQ0 to IRQ3, IRQ6, and IRQ7. Set the IRQ sense select bits (IRQ0S to IRQ3S, IRQ6S, and IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A and B (IPRA, IPRB). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F to IRQ3F, IRQ6F, and IRQ7F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request detection results are maintained until the interrupt request is accepted. Confirmation that IRQ interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F to IRQ3F, IRQ6F, and IRQ7F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt.
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6.2.3
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: * * * * * * Multifunction timer pulse unit (MTU) Compare match timer (CMT) Serial communications interface (SCI1) A/D converter (A/D) Watchdog timer (WDT) 8-bit timer 2 (TIM2)
A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers C to H (IPRC to IPRH). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.4 Interrupt Exception Vectors and Priority Rankings
Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. See section 5 Exception Processing, table 5.4, Calculating Exception Processing Vector Table Addresses. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to H (IPRA to IPRH). The ranking of interrupt sources for IPRC to IPRH, however, must be the order listed under Priority Order Within IPR Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3.
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Table 6.3
Interrupt Exception Processing Vectors and Priorities
Interrupt Vector Vector No. 11 64 65 66 67 70 71 TGI0A TGI0B TGI0C TGI0D TCI0V 88 89 90 91 92 96 97 100 Vector Table Address Offset Interrupt Priority (Initial Value) Priority within IPR Setting Default Range Priority -- -- -- -- -- -- -- High High
Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7 MTU0
Corresponding IPR (Bits) -- IPRA (15 to 12) IPRA (11 to 8) IPRA (7 to 4) IPRA (3 to 0) IPRB (7 to 4) IPRB (3 to 0) IPRD (15 to 12)
H'0000002C to 16 H'0000002F H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
H'0000010C to 0 to 15 (0) H'0000010F H'00000118 to H'0000011B 0 to 15 (0)
H'0000011C to 0 to 15 (0) H'0000011F H'00000160 to H'00000163 H'00000164 to H'00000167 H'00000168 to H'0000016B 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
H'0000016C to 0 to 15 (0) H'0000016F H'00000170 to H'00000173 H'00000180 to H'00000183 H'00000184 to H'00000187 H'00000190 to H'00000193 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRD (3 to 0) IPRD (11 to 8) IPRD (7 to 4)
Low -- High Low -- Low
MTU1
TGI1A TGI1B TCI1V
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Table 6.3
Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Vector Vector No. 104 105 108 132 133 134 135 138 144 148 152 153 Vector Table Address Offset Interrupt Priority (Initial Value) Priority within IPR Setting Default Range Priority High Low IPRE (11 to 8) IPRF (3 to 0) -- High High
Interrupt Source MTU2 TGI2A TGI2B TCI2V SCI1 ERI1 RXI1 TXI1 TEI1 A/D CMT0 CMT1 WDT TIM2 ADI CMI0 CMI1 ITI CMI
Corresponding IPR (Bits) IPRE (15 to 12)
H'000001A0 to 0 to 15 (0) H'000001A3 H'000001A4 to 0 to 15 (0) H'000001A7 H'000001B0 to 0 to 15 (0) H'000001B3 H'00000210 to H'00000213 H'00000214 to H'00000217 H'00000218 to H'0000021B H'0000021C to H'0000021F H'00000228 to H'0000022B H'00000240 to H'00000243 H'00000250 to H'00000253 H'00000260 to H'00000263 H'00000264 to H'00000267 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
Low IPRG (15 to 12) IPRG (7 to 4) IPRG (3 to 0) IPRH (15 to 2) -- -- -- High Low Low
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6.3
6.3.1
Description of Registers
Interrupt Priority Registers A to H (IPRA to IPRH)
Interrupt priority registers A to H (IPRA to IPRH) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA to IPRH bits is shown in table 6.4.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Table 6.4
Interrupt Request Sources and IPRA to IPRH
Bits
Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H
15 to 12 IRQ0 Reserved Reserved MTU0 MTU2 Reserved A/D WDT, TIM2
11 to 8 IRQ1 Reserved Reserved MTU0 MTTU2 Reserved Reserved Reserved
7 to 4 IRQ2 IRQ6 Reserved MTU1 Reserved Reserved CMT0 Reserved
3 to 0 IRQ3 IRQ7 Reserved MTU1 Reserved SCI1 CMT1 Reserved
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. 8-bit timers 1 and 2 are set to the same priority rank.
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IPRA to IPRH are initialized to H'0000 by a power-on reset. Reserved bits are always read as 0. The write value should always be 0. It is not initialized in the standby mode. 6.3.2 Interrupt Control Register (ICR)
The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 to IRQ3, IRQ6, IRQ7 and indicates the input signal level to the NMI pin. A power-on reset initializes ICR. It is not initialized in the standby mode.
Bit: 15 NMIL Initial value: R/W: Bit: * R 7 IRQ0S Initial value: R/W: 0 R/W 14 -- 0 R 6 IRQ1S 0 R/W 13 -- 0 R 5 IRQ2S 0 R/W 12 -- 0 R 4 IRQ3S 0 R/W 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 IRQ6S 0 R/W 8 NMIE 0 R/W 0 IRQ7S 0 R/W
Note: * When NMI input is high: 1; when NMI input is low: 0
* Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL 0 1 Description NMI input level is low NMI input level is high
* Bits 14 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--NMI Edge Select (NMIE)
Bit 8: NMIE 0 1 Description Interrupt request is detected on falling edge of NMI input (Initial value) Interrupt request is detected on rising edge of NMI input
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* Bits 7 to 4, 1, and 0--IRQ0 to IRQ3, IRQ6, and IRQ7 Sense Select (IRQ0S to IRQ3S, IRQ6S, IRQ7S): These bits set the IRQ0 to IRQ7 interrupt request detection mode.
Bits 7 to 4, 1, 0: IRQ0S to IRQ3S, IRQ6S, IRQ7S 0 1
Description Interrupt request is detected on low level of IRQ input Interrupt request is detected on falling edge of IRQ input (Initial value)
* Bits 3 and 2--Reserved: These bits always read as 0. The write value should always be 0. 6.3.3 IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3, IRQ6, and IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1. A power-on reset initializes ISR. It is not initialized in the standby mode.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IRQ0F Initial value: R/W: 0 R/W 14 -- 0 R 6 IRQ1F 0 R/W 13 -- 0 R 5 IRQ2F 0 R/W 12 -- 0 R 4 IRQ3F 0 R/W 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 IRQ6F 0 R/W 8 -- 0 R 0 IRQ7F 0 R/W
* Bits 15 to 8, 3, and 2--Reserved: These bits are always read as 0. The write value should always be 0.
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* Bits 7 to 4, 1, and 0--IRQ0 to IRQ3, IRQ6, and IRQ7 Flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F): These bits display the IRQ0 to IRQ3, IRQ6, IRQ7 interrupt request status.
Bits 7 to 4, 1, 0: IRQ0F to IRQ3F, IRQ6F, IRQ7F Detection Setting Description 0 Level detection No IRQn interrupt request exists. Clear conditions: When IRQn input is high level Edge detection No IRQn interrupt request was detected. Clear conditions: 1. When a 0 is written after reading IRQnF = 1 status 2. When IRQn interrupt exception processing has been executed 1 Level detection An IRQn interrupt request exists. Set conditions: When IRQn input is low level Edge detection An IRQn interrupt request was detected. Set conditions: When a falling edge occurs at an IRQn input (Initial value)
ISR.IRQnF IRQnS (0: level, 1: edge) IRQ pin Level detection Edge detection SQ CPU interrupt request
Selection
RESIRQn
R
(IRQn interrupt acceptance/IRQnF = 0 write after IRQnF = 1 read)
Figure 6.2 External Interrupt Process
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6.4
6.4.1
Interrupt Operation
Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers A to H (IPRA to IPRH). Lower-priority interrupts are ignored*. If a number of interrupts with the same priority level occur, or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting range (as indicated in table 6.3) is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The interrupt controller detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.5). 5. The status register (SR) and program counter (PC) are saved onto the stack. 6. The priority level of the accepted interrupt is written to bits I3 to I0 in SR. 7. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. Note: An interrupt request for which edge detection has been set is held pending until it is accepted. However, an IRQ interrupt can be cleared by an IRQ status register (ISR) access. For details see section 6.2.2, IRQ Interrupts. Pending edge-detected interrupts are cleared by a power-on reset.
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Program execution state No
Interrupt? Yes NMI? Yes
No
Level 15 interrupt? Yes Yes I3 to I0 level 14? No Yes
No
Level 14 interrupt? Yes I3 to I0 level 13? No Yes
No Level 1 interrupt? Yes I3 to I0 = level 0? No No
Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 Reads exception vector table Branches to exception service routine
I3 to I0: Interrupt mask bits of status register
Figure 6.3 Interrupt Sequence Flowchart
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6.4.2
Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address 4n-8 4n-4 4n PC*1 SR 32 bits 32 bits SP*2
Notes: 1. 2.
PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
6.5
Interrupt Response Time
Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is accepted.
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Table 6.5
Interrupt Response Time
Number of States
Item Compare identified interrupt priority with SR mask level Wait for completion of sequence currently being executed by CPU
NMI, Peripheral Module 2
IRQ 3
Notes
X ( 0)
The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the PC and SR saves and vector address fetch.
Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt response time Total 7 + m1 + m2 + m3 Minimum 10 Maximum 12 + 2 (m1 + m2 + m3) + m4 9 + m1 + m2 + m3 12 13 + 2 (m1 + m2 + m3) + m4
20 MHz operation: 0.5 to 0.6 s 20 MHz operation: 0.95 to 1.0 s*
Note: * When m1 = m2 = m3 = m4 = 1 m1 to m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine
73
Interrupt acceptance 5 + m1 + m2 + m3 m1 m2 1 m3 1 3 1 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction FDEEMMEMEE 3
F FDE
F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed).
Figure 6.5 Pipeline when an IRQ Interrupt is Accepted
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Section 7 Bus State Controller (BSC)
7.1 Overview
The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the LSI without external circuitry. 7.1.1 Features
* Address space is divided into four spaces A maximum linear 2 Mbytes for address space CS0 A maximum linear 4 Mbytes for each of address spaces CS1 to CS3 8-bit bus width Wait states can be inserted by software for each space (0 to 3 waits) In external memory space access, wait states can be inserted by the WAIT pin Outputs control signals for each space according to the type of memory connected * RAM interface On-chip RAM access of 32 bits in 1 state
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7.1.2
Block Diagram
Figure 7.1 shows the BSC block diagram.
Bus interface
WAIT
Wait control unit
WCR1
BCR1 CS0 to CS3 Module bus Area control unit BCR2
RD Memory control unit
WRL
BSC WCR1: Wait control register 1 BCR1: Bus control register 1 BCR2: Bus control register 2
Figure 7.1 BSC Block Diagram
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Internal bus
7.1.3
Pin Configuration
Table 7.1 shows the bus state controller pin configuration. Table 7.1
Pin Name A21 to A0 D7 to D0 CS0 to CS3 RD WRL WAIT
Pin Configuration
I/O Output I/O Output Output Output Input Function Address output 8-bit data bus Chip select Strobe that indicates a read cycle for ordinary space/multiplex I/O Strobe that indicates a write cycle Wait state request signal
7.1.4
Register Configuration
The bus state controller has three registers. The functions of these registers include control of wait states and interfaces with memories such as ROM and SRAM. The registers are summarized in table 7.2. Both registers are 16 bits in size, and are initialized by a power-on reset. Table 7.2
Name Bus control register 1 Bus control register 2 Wait state control register 1
Register Configuration
Abbr. BCR1 BCR2 WCR1 R/W R/W R/W R/W Initial Value Address H'200F H'FFFF H'FFFF Access Size
H'FFFF8620 8, 16 H'FFFF8622 8, 16 H'FFFF8624 8, 16
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7.1.5
Address Map
Figure 7.2 shows the address format used by this LSI.
A31
A24
A23, A22
A21
A0
Output address: Output from the address pins CS space selection: Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS space when 00000000 (H'00) Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 7.2 Address Format This LSI uses 32-bit addresses: * A31 to A24 are used to select the type of space and are not output externally. * Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits A31 to A24 are 00000000. * A21 to A0 are output externally. Table 7.3 shows an address map.
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Table 7.3
Address
Address Map
Space Memory Size Bus Width
H'00000000 to H'00027FFF H'00028000 to H'001FFFFF H'00200000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF H'01000000 to H'FFFF7FFF H'FFFF8000 to H'FFFF87FF
On-chip ROM On-chip ROM Reserved CS0 space CS1 space CS2 space CS3 space Reserved On-chip peripheral module Reserved Reserved Ordinary space Ordinary space Ordinary space Ordinary space Reserved On-chip peripheral module Reserved
160 kbytes 32 bits
2 Mbytes 4 Mbytes 4 Mbytes 4 Mbytes
8 bits 8 bits 8 bits 8 bits
2 kbytes
8/16 bits
H'FFFF8800 to H'FFFFEFFF H'FFFFF000 to H'FFFFFFFF
On-chip RAM On-chip RAM
4 kbytes
32 bits
Note: Do not access reserved spaces. Operation cannot be guaranteed if they are accessed.
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7.2
7.2.1
Description of Registers
Bus Control Register 1 (BCR1)
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 1 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 A3SZ 1 R/W 10 -- 0 R 2 A2SZ 1 R/W 9 -- 0 R 1 A1SZ 1 R/W 8 -- 0 R 0 A0SZ 1 R/W
Note: Never write 1 to bits 4 to 7; doing so can result in unstable operation.
Bus control register 1 (BCR1) is a 16-bit readable/writeable register that specifies the bus size for each CS space. Note that this chip requires that byte bus size (8 bits). Initial settings should be written to bits 8 to 0 of BCR1 following a power-on reset, and the values should then be left unchanged. Also, the CS spaces should not be accessed until initial setting of the registers has been completed. BCR1 is initialized to H'200F by a power-on reset. It is not initialized in the standby mode. * Bits 15, 14, and 12 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 13--Reserved: This bit is always read as 1. The write value should always be 1. * Bit 3--CS3 Space Size Specification (A3SZ): Specifies the bus size for CS3. The SH7018 requires a byte bus size, so this bit must always be set to 0.
Bit 3: A3SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value)
80
* Bit 2--CS2 Space Size Specification (A2SZ): Specifies the bus size for CS2. The SH7018 requires a byte bus size, so this bit must always be set to 0.
Bit 2: A2SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value)
* Bit 1--CS1 Space Size Specification (A1SZ): Specifies the bus size for CS1. The SH7018 requires a byte bus size, so this bit must always be set to 0.
Bit 1: A1SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value)
* Bit 0--CS0 Space Size Specification (A0SZ): Specifies the bus size for CS0. The SH7018 requires a byte bus size, so this bit must always be set to 0.
Bit 0: A0SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value)
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7.2.2
Bus Control Register 2 (BCR2)
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized by power-on resets to H'FFFF.
Bit: 15 IW31 Initial value: R/W: Bit: 1 R/W 7 CW3 Initial value: R/W: 1 R/W 14 IW30 1 R/W 6 CW2 1 R/W 13 IW21 1 R/W 5 CW1 1 R/W 12 IW20 1 R/W 4 CW0 1 R/W 11 IW11 1 R/W 3 SW3 1 R/W 10 IW10 1 R/W 2 SW2 1 R/W 9 IW01 1 R/W 1 SW1 1 R/W 8 IW00 1 R/W 0 SW0 1 R/W
* Bits 15 to 8--Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with the area specification of the previous access. Refer to section 7.4, Waits between Access Cycles, for details. IW31 and IW30 specify the idle between cycles for the CS3 space; IW21 and IW20 specify the idle between cycles for the CS2 space; IW11 and IW10 specify the idle between cycles for the CS1 space, and IW01 and IW00 specify the idle between cycles for the CS0 space.
Bit 15 (IW31) 0 Bit 14 (IW30) 0 1 1 0 1 Description No idle cycle after accessing CS3 space Inserts one idle cycle after accessing CS3 space Inserts two idle cycles after accessing CS3 space Inserts three idle cycles after accessing CS3 space (Initial value)
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Bit 13 (IW21) 0
Bit 12 (IW20) 0 1
Description No idle cycle after accessing CS2 space Inserts one idle cycle after accessing CS2 space Inserts two idle cycles after accessing CS2 space Inserts three idle cycles after accessing CS2 space (Initial value) Description No idle cycle after accessing CS1 space Inserts one idle cycle after accessing CS1 space Inserts two idle cycles after accessing CS1 space Inserts three idle cycles after accessing CS1 space (Initial value) Description No idle cycle after accessing CS0 space Inserts one idle cycle after accessing CS0 space Inserts two idle cycles after accessing CS0 space Inserts three idle cycles after accessing CS0 space (Initial value)
1
0 1
Bit 11 (IW11) 0
Bit 10 (IW10) 0 1
1
0 1
Bit 9 (IW01) 0
Bit 8 (IW00) 0 1
1
0 1
* Bits 7 to 4--Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when doing consecutive accesses of the same CS space. When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IW and CW. Refer to section 7.4, Waits between Access Cycles, for details. CW3 specifies the continuous access idles for the CS3 space; CW2 specifies the continuous access idles for the CS2 space; CW1 specifies the continuous access idles for the CS1 space and CW0 specifies the continuous access idles for the CS0 space.
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Bit 7 (CW3) 0 1
Description No CS3 space continuous access idle cycles One CS3 space continuous access idle cycle (Initial value)
Bit 6 (CW2) 0 1
Description No CS2 space continuous access idle cycles One CS2 space continuous access idle cycle (Initial value)
Bit 5 (CW1) 0 1
Description No CS1 space continuous access idle cycles One CS1 space continuous access idle cycle (Initial value)
Bit 4 (CW0) 0 1
Description No CS0 space continuous access idle cycles One CS0 space continuous access idle cycle (Initial value)
* Bits 3 to 0--CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal or WRL signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time. Refer to section 7.3.3, CS Assert Period Extension, for details. SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access.
Bit 3 (SW3) 0 1 Description No CS3 space CS assert extension CS3 space CS assert extension Description No CS2 space CS assert extension CS2 space CS assert extension (Initial value) (Initial value)
Bit 2 (SW2) 0 1
84
Bit 1 (SW1) 0 1
Description No CS1 space CS assert extension CS1 space CS assert extension Description No CS0 space CS assert extension CS0 space CS assert extension (Initial value) (Initial value)
Bit 0 (SW0) 0 1
85
7.2.3
Wait Control Register 1 (WCR1)
Wait control register 1 (WCR1) is a 16-bit read/write register that specifies the number of wait cycles (0 to 3) for each CS space. WCR1 is initialized to H'FFFF by power-on resets.
Bit: 15 -- Initial value: R/W: Bit: 1 R 7 -- Initial value: R/W: 1 R 14 -- 1 R 6 -- 1 R 13 W31 1 R/W 5 W11 1 R/W 12 W30 1 R/W 4 W10 1 R/W 11 -- 1 R 3 -- 1 R 10 -- 1 R 2 -- 1 R 9 W21 1 R/W 1 W01 1 R/W 8 W20 1 R/W 0 W00 1 R/W
* Bits 15 and 14--Reserved: These bits are always read as 1. The write value should always be 1. * Bits 13 and 12--CS3 Space Wait Specification (W31, W30): These bits specify the number of waits for CS3 space accesses.
Bit 13 (W31) 0 Bit 12 (W30) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (Initial value)
* Bits 11 and 10--Reserved: These bits are always read as 1. The write value should always be 1.
86
* Bits 9 and 8--CS2 Space Wait Specification (W21, W20): These bits specify the number of waits for CS2 space accesses.
Bit 9 (W21) 0 Bit 8 (W20) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (Initial value)
* Bits 7 and 6--Reserved. Either 0 or 1 can be written. These bits read the written value. * Bits 5 and 4--CS1 Space Wait Specification (W11, W10): These bits specify the number of waits for CS1 space accesses.
Bit 5 (W11) 0 Bit 4 (W10) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (Initial value)
* Bits 3 and 2--Reserved. Either 0 or 1 can be written. These bits read the written value. * Bits 1 and 0--CS0 Space Wait Specification (W01, W00): These bits specify the number of waits for CS0 space accesses.
Bit 1 (W01) 0 Bit 0 (W00) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (Initial value)
87
7.3
Accessing Ordinary Space
A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 7.3.1 Basic Timing
Figure 7.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are performed in 2 states.
T1 CK T2
Address
CSn RD Read Data
WRL Write Data
Figure 7.3 Basic Timing of Ordinary Space Access During a read, irrespective of operand size, all bits in the data bus width for the access space (address) are fetched by the LSI on RD, using the required byte locations. During a write, the following signals are associated with transfer of these actual byte locations: WRL (bits 7 to 0).
88
7.3.2
Wait State Control
The number of wait states inserted into ordinary space access states can be controlled using the WCR settings. The specified number of Tw cycles (0 to 3 waits) are inserted as software wait cycles with the timing shown in figure 7.4.
T1 CK TW T2
Address CSn RD Read Data
WRL Write Data
Figure 7.4 Wait Timing of Ordinary Space Access (Software Wait Only)
89
When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 7.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when T w state shifts to T2 state.
T1 CK Address CSn TW TW TW0 T2
RD Read Data WRL Write Data WAIT
Figure 7.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2 State + WAIT Signal)
90
7.3.3
CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD signal or WRL signal assert period beyond the length of the CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 7.6. Th and T f cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD and WRL signals are not. Further, data is extended up to the Tf cycle, which is effective for gate arrays and the like, which have slower write operations.
Th CK T1 T2 Tf
Address CSn RD Read Data
WRL Write Data
Figure 7.6 CS Assert Period Extension Function
91
7.4
Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once. 7.4.1 Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of the BCR2 is inserted. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles is inserted. Figure 7.7 shows an example of idles between cycles. In this example, 1 idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, 1 idle cycle is inserted.
T1 CK Address T2 Tidle T1 T2
CSn CSm
RD WRL Data
CSn space read
Idle cycle
CSm space write
Figure 7.7 Idle Cycle Insertion Example
92
IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 cycles can be specified for CS space. 7.4.2 Simplification of Bus Cycle Start Detection
For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of the BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 7.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write accessed.
T1 CK Address T2 Tidle T1 T2
CSn
RD WRL Data
CSn space access
Idle cycle
CSn space access
Figure 7.8 Same Space Consecutive Access Idle Cycle Insertion Example
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7.5
Memory Connection Examples
256k x 8 bits ROM CSn RD Axx D0 to D7 CE OE Axx I/O0 to I/O7
SH7018
Figure 7.9 8-Bit Data Bus Width ROM Connection
128k x 8 bits SRAM CS OE Axx WE I/O0 to I/O7
SH7018 CSn RD Axx WRL D0 to D7
Figure 7.10 8-Bit Data Bus Width SRAM Connection
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Section 8 Multifunction Timer Pulse Unit (MTU)
8.1 Overview
The SH7018 has an on-chip 16-bit multifunction timer pulse unit (MTU) with three channels of 16-bit timers. 8.1.1 Features
* Can process a maximum of six different pulse outputs and inputs. * Has eight timer general registers (TGR), four for channel 0 and two each for channels 1 and 2, that can be set to function independently as output compare registers or (except for TGR0B and TGR0D of channel 0) as input capture registers. The channel 0 TGRC and TGRD registers can be used as buffer registers. * Can select six counter input clock sources for all channels * All channels can be set for the following operating modes: Compare match waveform output: 0 output/1 output/toggle output selectable. Input capture function: Selectable rising edge, falling edge, or both rising and falling edge detection. Counter clearing function: Counters can be cleared by a compare-match or input capture. Synchronizing mode: Two or more timer counters (TCNT) can be written to simultaneously. Two or more timer counters can be simultaneously cleared by a comparematch or input capture. Counter synchronization functions enable synchronized register input/output. PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, enables up to four-phase* PWM output. Note: * When channels 0 to 2 are set to PWM mode 1 * Channel 0 can be set for buffer operation Input capture register double buffer configuration possible Output compare register automatic re-write possible * Cascade connection operation Can be operated as a 32-bit counter by using the channel 2 input clock for channel 1 overflow/underflow * High speed access via internal 16-bit bus * Eleven interrupt sources Channel 0 has two dual-function compare-match/input capture interrupts, two comparematch interrupts, and one overflow interrupt, which can be requested independently.
95
Channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. * A/D converter conversion start trigger can be generated Channel 0 to 2 compare-match/input capture signals can be used as A/D converter conversion start triggers.
96
Table 8.1 summarizes the MTU functions. Table 8.1
Item Counter clocks General registers
MTU Functions
Channel 0 Channel 1 Channel 2
Internal: /1, /4, /16, /64, /256, /1024 Six to each channel TGR0A TGR0B TGR1A TGR1B No TGR2A TGR2B No
General registers/buffer registers Input/output pins
TGR0C TGR0D TIOC0A TIOC0C
TIOC1A TIOC1B
TIOC2A TIOC2B
Counter clear function Compare match output 0 1 Toggle
TGR compare-match or TGR compare-match or TGR compare-match or input capture input capture input capture Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes No Yes Yes
Input capture function Synchronization Buffer operation PWM mode 1 PWM mode 2
A/D conversion start TGR0A compare match TGR1A compare match TGR2A compare match trigger or input capture or input capture or input capture Interrupt sources Compare match/input capture 0A Compare match 0B Compare match/input capture 0C Compare match 0D Overflow Compare match/input capture 1A Compare match/input capture 1B Overflow -- -- Compare match/input capture 2A Compare match/input capture 2B Overflow -- --
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8.1.2
Block Diagram
Figure 8.1 is the block diagram of the MTU.
[Clock input] Internal clock: /1 /4 /16 /64 /256 /1024
Control logic
TSYR
Internal data bus
BUS I/F
Shared
Channel 2 TCR TMDR
TSR
TSTR
A/D conversion start request signal
TGRA
TGRB
TCNT
Channel 0 to 2 control logic
Channel 1 TCR TMDR
TSR
[I/O pins] Channel 0: TIOC0A TIOC0C Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B
TGRA
TIOR
TIER
TGRB
TCNT
[Interrupt request signal] Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V
TGRC TGRD
TIOR
TIER
TIORH TIORL
Channel 0 TCR TMDR
TSR
Module data bus
TGRA
TGRB
TCNT
Channel 2: TGI2A TGI2B TCI2V
Figure 8.1 MTU Block Diagram
98
TIER
8.1.3
Pin Configuration
Table 8.2 summarizes the MTU pins. Table 8.2 Pin Configuration
Pin Name I/O Function I/O TGR0A input capture input/output compare output/PWM output pin I/O TGR0C input capture input/output compare output/PWM output pin I/O TGR1A input capture input/output compare output/PWM output pin I/O TGR1B input capture input/output compare output/PWM output pin I/O TGR2A input capture input/output compare output/PWM output pin I/O TGR2B input capture input/output compare output/PWM output pin
Channel Name 0
Input TIOC0A capture/output compare-match 0A Input TIOC0C capture/output compare-match 0C
1
Input TIOC1A capture/output compare-match 1A Input TIOC1B capture/output compare-match 1B
2
Input TIOC2A capture/output compare-match 2A Input TIOC2B capture/output compare-match 2B
Note: The TIOC pins output undefined values when they are set to input capture and timer output by the pin function controller (PFC).
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8.1.4
Register Configuration
Table 8.3 summarizes the MTU register configuration. Table 8.3 Register Configuration
Abbreviation R/W TSTR TSYR TCR0 TMDR0 R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'C0 H'00 H'00 H'40 Address H'FFFF8240 H'FFFF8241 H'FFFF8260 H'FFFF8261 H'FFFF8262 H'FFFF8263 H'FFFF8264 H'FFFF8265 H'FFFF8266 H'FFFF8268 H'FFFF826A H'FFFF826C H'FFFF826E H'FFFF8280 H'FFFF8281 H'FFFF8282 H'FFFF8284 H'FFFF8285 H'FFFF8286 H'FFFF8288 H'FFFF828A 16, 32 8 8, 16, 32 8, 16 16, 32 8, 16, 32 Access Size (Bits)* 1 8, 16
Channel Name Shared Timer start register Timer synchro register 0 Timer control register 0 Timer mode register 0
Timer I/O control register 0H TIOR0H R/W Timer I/O control register 0L TIOR0L R/W Timer interrupt enable register 0 Timer status register 0 Timer counter 0 General register 0A General register 0B General register 0C General register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 General register 1A General register 1B TIER0 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR1A TGR1B R/W
R/(W)*2 H'C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40
R/(W)*2 H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF
100
Table 8.3
Register Configuration (cont)
Abbreviation R/W TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B R/W R/W R/W R/W Initial Value H'00 H'C0 H'00 H'40 Address H'FFFF82A0 H'FFFF82A1 H'FFFF82A2 H'FFFF82A4 H'FFFF82A5 H'FFFF82A6 H'FFFF82A8 H'FFFF82AA 16, 32 8 8, 16, 32 Access Size (Bits)* 1 8, 16
Channel Name 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 General register 2A General register 2B
R/(W)*2 H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF
Notes: Do not access empty addresses. 1. 16-bit registers (TCNT, TGR) cannot be read or written in 8-bit units. 2. Write 0 to clear flags.
8.2
8.2.1
MTU Register Descriptions
Timer Control Register (TCR)
The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The MTU has three TCR registers, one for each of the channels 0 to 2. TCR is initialized to H'00 by a power-on reset or the standby mode. Channel 0: TCR0
Bit: 7 CCLR2 Initial value: R/W: 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 3 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 CKEG0 0 R/W 0 R/W
Channels 1 and 2: TCR1, TCR2
Bit: 7 -- Initial value: R/W: 0 R 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 3 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 CKEG0 0 R/W 0 R/W
101
* Bits 7 to 5--Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): Select the counter clear source for the TCNT counter. Channel 0:
Bit 7: Bit 6: CCLR2 CCLR1 0 0 Bit 5: CCLR0 0 1 1 0 1 1 0 0 1 1 0 1 Description TCNT clear disabled (Initial value)
TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync* 1 TCNT clear disabled TCNT is cleared by TGRC compare-match or input capture* 2 TCNT is cleared by TGRD compare-match* 2 Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync* 1
Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization. 2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because the buffer registers have priority and compare-match/input captures do not occur.
Channels 1 and 2:
Bit 7: Bit 6: Reserved* 1 CCLR1 0 0 Bit 5: CCLR0 0 1 1 0 1 Description TCNT clear disabled (Initial value)
TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync* 2
Notes: 1. The bit 7 of channels 1 and 2 is reserved. This bit is always read as 0. The write value should always be 0. 2. Setting the SYNC bit of the TSYR to 1 sets the synchronization.
* Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): CKEG1 and CKEG0 select the input clock edges. When counting is done on both edges of the internal clock the input clock frequency becomes 1/2 (Example: both edges of /4 = rising edge of /2).
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Bit 4: Bit 3: CKEG1 CKEG0 Description 0 0 1 1 X Count on rising edges Count on falling edges Count on both rising and falling edges (Initial value)
Notes: 1. X: 0 or 1, don't care. 2. Internal clock edge selection is effective when the input clock is /4 or slower. These settings are ignored when /1, or the overflow of another channel is selected for the input clock.
* Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2 to TPSC0): TPSC2 to TPSC0 select the counter clock source for the TCNT. An independent clock source can be selected for each channel. Table 8.4 shows the possible settings for each channel. Table 8.4 MTU Clock Sources
Internal Clock Channel 0 1 2 /1 O O O /4 O O O /16 O O O /64 O O O /256 X O X /1024 X X O Other Channel Overflow X O X
Note: Symbols: O: Setting possible
X: Setting not possible
Channel 0:
Bit 2: Bit 1: TPSC2 TPSC1 0 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with /1 Internal clock: count with /4 Internal clock: count with /16 Internal clock: count with /64 Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) (Initial value)
103
Channel 1:
Bit 2: Bit 1: TPSC2 TPSC1 0 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with /1 Internal clock: count with /4 Internal clock: count with /16 Internal clock: count with /64 Reserved (Do not set) Reserved (Do not set) Internal clock: count with /256 Count with the TCNT2 overflow (Initial value)
Channel 2:
Bit 2: Bit 1: TPSC2 TPSC1 0 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with /1 Internal clock: count with /4 Internal clock: count with /16 Internal clock: count with /64 Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) Internal clock: count with /1024 (Initial value)
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8.2.2
Timer Mode Register (TMDR)
The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset. Channel 0: TMDR0
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
Channels 1 and 2: TMDR1, TMDR2
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 0 R 4 -- 0 R 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
* Bits 7 and 6--Reserved: These bits are always read as 1. The write value should always be 1. * Bit 5--Buffer Operation B (BFB): Designates whether to use the TGRB register for normal operation, or buffer operation in combination with the TGRD register. When using TGRD as a buffer register, no TGRD register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRD registers. It is always read as 0. The write value should always be 0.
Bit 5: BFB 0 1 Description TGRB operates normally TGRB and TGRD buffer operation (Initial value)
* Bit 4--Buffer Operation A (BFA): Designates whether to use the TGRA register for normal operation, or buffer operation in combination with the TGRC register. When using TGRC as a buffer register, no TGRC register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0. The write value should always be 0.
Bit 4: BFA 0 1 Description TGRA operates normally TGRA and TGRC buffer operation (Initial value)
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* Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits set the timer operation mode.
Bit 3: MD3 0 Bit 2: MD2 0 Bit 1: MD1 0 Bit 0: MD0 0 1 1 0 1 0 1 1 * * * * * Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2 Reserved (Do not set) Reserved (Do not set) (Initial value)
*: Don't care
8.2.3
Timer I/O Control Register (TIOR)
The TIOR is a register that controls the TGR. The MTU has four TIOR registers, two for channel 0, and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on reset. Channel 0: TIOR0H
Bit: 7 -- Initial value: R/W: 0 R 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W
Channels 1 and 2: TIOR1, TIOR2
Bit: 7 IOB3 Initial value: R/W: 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W
Bits 7 to 4--I/O Control B3 to B0 (IOB3 to IOB0): These bits set the TGRB register function. Bit 7 of TIOR0H is reserved bit. It is always read as 0. The write value should always be 0. Bits 3 to 0--I/O Control A3 to A0 (IOA3 to IOA0): These bits set the TGRA register function.
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Channel 0: TIOR0L
Bit: 7 -- Initial value: R/W: 0 R 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W
Note: When the TGRC or TGRD registers are set for buffer operation, these settings become ineffective and the operation is as a buffer register.
* Bit 7--Reserved. This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--I/O Control D2 to D0 (IOD2 to IOD0): These bits set the TGRD register function. * Bits 3 to 0--I/O Control C3 to C0 (IOC3 to IOC0): These bits set the TGRC register function. Channel 0 (TIOR0H Register):
Bit 6: IOB2 0 Bit 5: Bit 4: IOB1 IOB0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description TGR0B is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
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Bit 3: IOA3 0
Bit 2: Bit 1: IOA2 IOA1 0 0
Bit 0: IOA0 Description 0 1 TGR0A is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 TGR0A is an input capture register Capture input source is the TIOC0A pin Capture input source is channel 1/ count clock Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Input capture on TCNT1 count up/count down
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Channel 0 (TIOR0L Register):
Bit 6: IOD2 0 Bit 5: Bit 4: IOD1 IOD0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description TGR0D is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Bit 3: IOC3 0
Bit 2: Bit 1: IOC2 IOC1 0 0
Bit 0: IOC0 Description 0 1 TGR0C is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 TGR0C is an input capture register Capture input source is the TIOC0C pin Capture input source is channel 1/ count clock Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Input capture on TCNT1 count up/count down
Note: When the BFA bit of TMDR0 is set to 1 and TGR0C is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur.
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Channel 1 (TIOR1 Register):
Bit 7: IOB3 0 Bit 6: Bit 5: IOB2 IOB1 0 0 Bit 4: IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR1B is an input capture register Description TGR1B is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC1B pin Capture input source TGR0C compare/match input capture Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on channel TGR0C compare-match/input capture generation
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Bit 3: IOA3 0
Bit 2: Bit 1: IOA2 IOA1 0 0
Bit 0: IOA0 Description 0 1 TGR1A is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 TGR1A is an input capture register Capture input source is the TIOC1A pin Capture input source is TGR0A comparematch/input capture Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Input capture on channel 0/TGR0A compare-match/input capture generation
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Channel 2 (TIOR2 Register):
Bit 7: IOB3 0 Bit 6: Bit 5: IOB2 IOB1 0 0 Bit 4: IOB0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR2B is an input capture register TGR2B is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC2B pin Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on rising edge Input capture on falling edge Input capture on both edges
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Bit 3: IOA3 0
Bit 2: Bit 1: IOA2 IOA1 0 0
Bit 0: IOA0 Description 0 1 TGR2A is an output compare register Output disabled Initial output is 0 Output disabled Initial output is 1 TGR2A is an input capture register Capture input source is the TIOC2A pin Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges (Initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
Input capture on rising edge Input capture on falling edge Input capture on both edges
1
0 1
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8.2.4
Timer Interrupt Enable Register (TIER)
The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel. The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a poweron reset. Channel 0: TIER0
Bit: 7 TTGE Initial value: R/W: 0 R/W 6 -- 1 R 5 -- 0 R 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
Channels 1 and 2: TIER1, TIER2
Bit: 7 TTGE Initial value: R/W: 0 R/W 6 -- 1 R 5 -- 0 R 4 TCIEV 0 R/W 3 -- 0 R 2 -- 0 R 1 TGIEB 0 R/W 0 TGIEA 0 R/W
* Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an A/D conversion start request by a TGRA register input capture/compare-match.
Bit 7: TTGE 0 1 Description Disable A/D conversion start requests generation Enable A/D conversion start request generation (Initial value)
* Bit 6--Reserved: This bit is always read as 1. The write value should always be 1. * Bit 5--Reserved. This bit is always read as 0. The write value should always be 0. * Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the overflow flag TCFV of the timer status register (TSR) is set to 1.
Bit 4: TCIEV 0 1 Description Disable TCFV interrupt requests (TCIV) Enable TCFV interrupt requests (TCIV) (Initial value)
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* Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when the TGFD bit of the channel 0 of the TSR register is set to 0. This bit is reserved for channels 1 and 2. It is always read as 0. The write value should always be 0.
Bit 3: TGIED 0 1 Description Disable interrupt requests (TGID) due to the TGFD bit Enable interrupt requests (TGID) due to the TGFD bit (Initial value)
* Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables TGFC interrupt requests when the TGFC bit of the Channel 0 of the TSR register is set to 1. This bit is reserved for channels 1 and 2. It is always read as 0. The write value should always be 0.
Bit 2: TGIEC 0 1 Description Disable interrupt requests (TGIC) due to the TGFC bit Enable interrupt requests (TGIC) due to the TGFC bit (Initial value)
* Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables TGFB interrupt requests when the TGFB bit of the TSR register is set to 1.
Bit 1: TGIEB 0 1 Description Disable interrupt requests (TGIB) due to the TGFB bit Enable interrupt requests (TGIB) due to the TGFB bit (Initial value)
* Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables TGFA interrupt requests when the TGFA bit of the TSR register is set to 1.
Bit 0: TGIEA 0 1 Description Disable interrupt requests (TGIA) due to the TGFA bit Enable interrupt requests (TGIA) due to the TGFA bit (Initial value)
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8.2.5
Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset. Channel 0: TSR0
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 0 R 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Note: * Only 0 writes to clear the flags are possible.
Channels 1 and 2: TSR1, TSR2
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 0 R 4 TCFV 0 R/(W)* 3 -- 0 R 2 -- 0 R 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Note: * Only 0 writes to clear the flags are possible.
* Bits 7 and 6--Reserved: These bits are always read as 1. The write value should always be 1. * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter overflow.
Bit 4: TCFV 0 1 Description Clear condition: With TCFV =1, a 0 write to TCFV after reading it (Initial value) Set condition: When the TCNT value overflows (H'FFFF H'0000)
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* Bit 3--Output Compare Flag D (TGFD): This status flag indicates the occurrence of a channel 0 TGRD register compare-match. This bit is reserved in channels 1 and 2. It is always read as 0. The write value should always be 0.
Bit 3: TGFD 0 1 Description Clear condition: With TGFD = 1, a 0 write to TGFD following a read (Initial value) Set condition: When TCNT = TGRD while TGRD is functioning as an output compare register
* Bit 2--Input Capture/Output Compare Flag C (TGFC): This status flag indicates the occurrence of a Channel 0 TGRC register input capture or compare-match. This bit is reserved for channels 1 and 2. It is always read as 0. The write value should always be 0.
Bit 2: TGFC 0 1 Description Clear condition: With TGFC = 1, a 0 write to TGFC following a read (Initial value) Set conditions: * * When TGRC is functioning as an output compare register (TCNT = TGRC) When TGRC is functioning as input capture (the TCNT value is sent to TGRC by the input capture signal)
* Bit 1--Output Compare Flag B (TGFB): This status flag indicates the occurrence of a TGRB register compare-match.
Bit 1: TGFB 0 1 Description Clear condition: With TGFB = 1, a 0 write to TGFB following a read (Initial value) Set conditions: When TGRB is functioning as an output compare register (TCNT = TGRB)
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* Bit 0--Input Capture/Output Compare Flag A (TGFA): This status flag indicates the occurrence of a TGRA register input capture or compare-match.
Bit 0: TGFA 0 1 Description Clear condition: With TGFA = 1, a 0 write to TGFA following a read (Initial value) Set conditions: * * When TGRA is functioning as an output compare register (TCNT = TGRA) When TGRA is functioning as input capture (the TCNT value is sent to TGRA by the input capture signal)
8.2.6
Timer Counters (TCNT)
The timer counters (TCNT) are 16-bit counters, with one for each channel, for a total of three. The TCNT are initialized to H'0000 by a power-on reset. Accessing the TCNT counters in 8-bit units is prohibited. Always access in 16-bit units. Channel 0: TCNT0 Channel 1: TCNT1 Channel 2: TCNT2
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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8.2.7
Timer General Register (TGR)
Each timer general register (TGR) is a 16-bit register that can function as either an output compare register or an input capture register. There are a total of eight TGR, four each for channels 0 and two each for channels 1 and 2. The TGRC and TGRD of channels 0 can be set to operate as buffer registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB with TGRD. The TGRs are initialized to H'FFFF by a power-on reset. Accessing of the TGRs in 8-bit units is disabled; they may only be accessed in 16-bit units.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
8.2.8
Timer Start Register (TSTR)
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer counters (TCNT) of channels 0 to 2. TSTR is initialized to H'00 upon power-on reset.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
* Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 2 to 0--Counter Start 2 to 0 (CST2 to CST0): Select starting and stopping of the timer counters (TCNT). The corresponding between bits and channels is as follows: CST2: Channel 2 (TCNT2) CST1: Channel 1 (TCNT1) CST0: Channel 0 (TCNT0)
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Bit n: CSTn 0 1
Description TCNTn count is halted TCNTn counts (Initial value)
Note: n = 2 to 0. If 0 is written to a CST bit during operation with the TIOC pin in the output state, the counter stops, but the TIOC pin output compare output level is maintained. If a write is performed on the TIOR register while a CST bit is 0, the pin output level is updated to the set initial output value.
8.2.9
Timer Synchro Register (TSYR)
The timer synchro register (TSYR) is an 8-bit read/write register that selects independent or synchronous TCNT counter operation for channels 0 to 2. Channels for which 1 is set in the corresponding bit will be synchronized. TSYR is initialized to H'00 upon power-on reset.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 SYNC2 0 R/W 1 0
SYNC1 SYNC0 0 R/W 0 R/W
* Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 2 to 0--Timer Synchronization 2 to 0 (SYNC2 to SYNC0): Selects operation independent of, or synchronized to, other channels. Synchronous operation allows synchronous clears due to multiple TCNT synchronous presets and other channel counter clears. A minimum of two channels must have SYNC bits set to 1 for synchronous operation. For synchronization clearing, it is necessary to set the TCNT counter clear sources (the CCLR2 to CCLR0 bits of the TCR register), in addition to the SYNC bit. The counter start to channel and bit-to-channel correspondence are indicated in the tables below. SYNC2: Channel 2 (TCNT2) SYNC1: Channel 1 (TCNT1) SYNC0: Channel 0 (TCNT0)
120
Bit n: SYNCn 0
Description Timer counter (TCNTn) independent operation (TCNTn preset/clear unrelated to other channels) Timer counter synchronous operation* 1 TCNTn synchronous preset/ synchronous clear* 2 possible (Initial value)
1 Note:
1. Minimum of two channel SYNC bits must be set to 1 for synchronous operation. 2. TCNT counter clear sources (CCLR2 to CCLR0 bits of the TCR register) must be set in addition to the SYNC bit in order to have clear synchronization. n = 2 to 0.
8.3
8.3.1
Bus Master Interface
16-Bit Registers
The timer counters (TCNT) and general registers (TGR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. Figure 8.2 shows an example of 16-bit register access operation.
Internal data bus Upper 8 bits Bus master Lower 8 bits TCNTH TCNTL Bus interface
Module data bus
Figure 8.2 16-Bit Register Access Operation (Bus Master TCNT (16 Bits)) 8.3.2 8-Bit Registers
All registers other than the TCNT and general registers (TGR) are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figure 8.3 to figure 8.5).
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Internal data bus Upper 8 bits Bus master Lower 8 bits Bus interface
Module data bus
TCR
Figure 8.3 8-Bit Register Access Operation (Bus Master TCR (Upper 8 Bits))
Internal data bus Upper 8 bits Bus master Lower 8 bits TMDR Bus interface
Module data bus
Figure 8.4 8-Bit Register Access Operation (Bus Master TMDR (Lower 8 Bits))
Internal data bus Upper 8 bits Bus master Lower 8 bits TCR TMDR Bus interface
Module data bus
Figure 8.5 8-Bit Register Access Operation (Bus Master TCR, TMDR (16 Bits))
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8.4
8.4.1
Operation
Overview
The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. General registers (TGR) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation does a synchronized preset. When any TCNT of a channel operating in the synchronized mode is rewritten, the TCNTs of other channels are simultaneously rewritten as well. The timer synchronization bits of the TSYR registers of multiple channels set for synchronous operation can be set to clear the TCNTs simultaneously. Buffer Operation: When TGR is an output compare register, the buffer register value of the corresponding channel is transferred to the TGR when a compare-match occurs. When TGR is an input capture register, the TCNT counter value is transferred to the TGR when an input capture occur simultaneously the value previously stored in the TGR is transferred to the buffer register. Cascade Connection Operation: The channel 1 and channel 2 counters (TCNT1 and TCNT2) can be connected together to operate as a 32-bit counter. PWM Mode: In PWM mode, a PWM waveform is output. The output level can be set by the TIOR register. Each TGR can be set for PWM waveform output with a duty cycle between 0% and 100%. 8.4.2 Basic Functions
Always select MTU external pin set function using the pin function controller (PFC). Counter Operation: When a start bit (CST0 to CST2) in the timer start register (TSTR) is set to 1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a freerunning mode and a periodic mode. To select the counting operation (figure 8.6): 1. Set bits TPSC2 to TPSC0 in the TCR to select the counter clock. At the same time, set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock. 2. To operate as a periodic counter, set the CCLR2 to CCLR0 bits in the TCR to select TGR as a clearing source for the TCNT.
123
3. Set the TGR selected in step 2 as an output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in the TGR selected in step 2. 5. Set the CST bit in the TSTR to 1 to start counting.
Counting mode selection Select counter clock (1)
Periodic counter Select counter clear source Select output compare register Set period Start counting Periodic counter
Free-running counter
(2)
(3)
(4) (5) Start counting Free-running counter (5)
Figure 8.6 Procedure for Selecting the Counting Operation Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves them all in the free-running mode. When a bit in the TSTR is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. When the count overflows from H'FFFF to H'0000, the TCFV bit in the timer status register (TSR) is set to 1. If the TCIEV bit in the timer's corresponding timer interrupt enable register (TIER) is set to 1, the MTU will make an interrupt request to the interrupt controller. After the TCNT overflows, counting continues from H'0000. Figure 8.7 shows an example of free-running counter operation.
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TCNT value H'FFFF
H'0000 Time CST bit TCFV
Figure 8.7 Free-Running Counter Operation Periodic Counter Operation Example: Periodic counter operation is obtained for a given channel's TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for period setting to output compare register and select counter clear upon compare-match using the CCLR2 to CCLR0 bits of the timer control register (TCR). After these settings, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTR is set to 1. When the count matches the TGR register value, the TGF bit in the TSR is set to 1 and the counter is cleared to H'0000. If the TGIE bit of the corresponding TIER is set to 1 at this point, the MTU will make an interrupt request to the interrupt controller. After the compare-match, TCNT continues counting from H'0000. Figure 8.8 shows an example of periodic counting.
TCNT value TGR Counter cleared by TGR compare match
H'0000 Time CST bit Flag cleared by software activation
TGF
Figure 8.8 Periodic Counter Operation
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Compare-Match Waveform Output Function: The MTU can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. Procedure for selecting the compare-match waveform output operation (figure 8.9): 1. Set the TIOR to select 0 output or 1 output for the initial value, and 0 output, 1 output, or toggle output for compare-match output. The TIOC pin will output the set initial value until the first compare-match occurs. 2. Set a value in the TGR to select the compare-match timing. 3. Set the CST bit in the TSTR to 1 to start counting.
Output selection Select waveform output mode Select output timing Start counting
(1)
(2)
(3)
Figure 8.9 Procedure for Selecting Compare Match Waveform Output Operation Waveform Output Operation (0 Output/1 Output): Figure 8.10 shows 0 output/1 output. In the example, TCNT is a free-running counter, 1 is output upon compare-match A and 0 is output upon compare-match B. When the pin level matches the set level, the pin level does not change.
126
TCNT value H'FFFF TGRA TGRB H'0000 TIOCA Time Does not change Does not change 1 output
TIOCB Does not change Does not change
0 output
Figure 8.10 Example of 0 Output/1 Output Waveform Output Operation (Toggle Output): Figure 8.11 shows the toggle output. In the example, the TCNT operates as a periodic counter cleared by compare-match B, with toggle output at both compare-match A and compare-match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB Time Toggle output Toggle output
TIOCA
Figure 8.11 Example of Toggle Output Input Capture Function: In the input capture mode, the TCNT value is transferred into the TGR register when the input edge is detected at the input capture/output compare pin (TIOC). Detection can take place on the rising edge, falling edge, or both edges. Channels 0 and 1 can use other channel counter input clocks or compare-match signals as input capture sources.
127
The procedure for selecting the input capture operation (figure 8.12) is: 1. Set the TIOR to select the input capture function of the TGR, then select the input capture source, and rising edge, falling edge, or both edges as the input edge. 2. Set the CST bit in the TSTR to 1 to start the TCNT counting.
Input selection Select input-capture input Start counting Input capture operation (1) (2)
Figure 8.12 Procedure for Selecting Input Capture Operation Input Capture Operation: Figure 8.13 shows input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to clear at the input capture of the TGRB register.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 TIOCA
Time
TGRA TIOCB
H'0005
H'0160
H'0010
TGRB
H'0180
Figure 8.13 Input Capture Operation
128
8.4.3
Synchronous Operation
There are two kinds of synchronous operation, synchronized preset and synchronized clear. The synchronized preset operation allows multiple timer counters (TCNT) to be rewritten simultaneously, while the synchronized clear operation allows multiple TCNT counters to be cleared simultaneously using timer control register (TCR) settings. The synchronizing mode can increase the number of TGR registers for a single time base. All five channels can be set for synchronous operation. Procedure for Selecting the Synchronizing Mode (Figure 8.14): 1. Set 1 in the SYNC bit of the timer synchro register (TSYR) to use the corresponding channel in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels. 3. Set the counter to clear with output compare/input capture using bits CCLR2 to CCLR0 in the TCR. 4. Set the counter clear source to synchronized clear using the CCLR2 to CCLR0 bits of the TCR. 5. Set the CST bits for the corresponding channels in the TSTR to 1 to start counting in the TCNT.
Select synchronizing mode
Set synchronizing mode
(1)
Synchronized preset
(2)
Synchronized clear
Set TCNT
Channel that generated clear source? Yes Select counter clear source
Start counting
No
(3)
Set counter synchronous clear
Start counting
(4)
(5)
(5)
Synchronized preset
Counter clear
Synchronized clear
Figure 8.14 Procedure for Selecting Synchronizing Operation
129
Synchronized Operation: Figure 8.15 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears by synchronous presets and TGR0B register compare-matches. Accordingly, a three-phase PWM waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A, TIOC1A, and TIOC2A pins. See section 8.4.6, PWM Mode, for details on the PWM mode.
TCNT0-TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 TIOC0A TIOC1A TIOC2A Time
Synchronized clear on TGR0B compare match
Figure 8.15 Synchronized Operation Example
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8.4.4
Buffer Operation
Buffer operation is a function of channel 0. TGRC and TGRD can be used as buffer registers. Table 8.5 shows the register combinations for buffer operation. Table 8.5
Channel 0
Register Combinations
General Register TGR0A TGR0B Buffer Register TGR0C TGR0D
The buffer operation differs, depending on whether the TGR has been set as an input capture register or an output compare register. When TGR Is an Output Compare Register: When a compare-match occurs, the corresponding channel buffer register value is transferred to the general register. Figure 8.16 shows an example.
Compare match signal Buffer register General register
Comparator
TCNT
Figure 8.16 Compare Match Buffer Operation When TGR Is an Input Capture Register: When an input capture occurs, the timer counter (TCNT) value is transferred to the general register (TGR), and the value that had been held up to that time in the TGR is transferred to the buffer register (figure 8.17).
Input capture signal
Buffer register
General register
TCNT
Figure 8.17 Input Capture Buffer Operation
131
Procedure for Setting Buffer Mode (Figure 8.18): 1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output compare register. 2. Use the timer mode register (TMDR) BFA, and BFB bits to set the TGR for buffer mode. 3. Set the CST bit in the TSTR to 1 to start the count operation.
Buffer mode
Select TGR function
(1)
Select buffer mode
(2)
Start counting
(3)
Buffer mode
Figure 8.18 Buffer Operation Setting Procedure Buffer Operation Examples--when TGR Is an Output Compare Register: Figure 8.19 shows an example of channel 0 set to PWM mode 1, and the TGRA and TGRC registers set for buffer operation. The TCNT counter is cleared by a compare-match B, and the output is a 1 upon compare-match A and 0 output upon compare-match B. Because buffer mode is selected, a compare-match A changes the output, and the buffer register TGRC value is simultaneously transferred to the general register TGRA. This operation is repeated with each occurrence of a compare-match A. See section 8.4.6, PWM Mode, for details on the PWM mode.
132
TCNT value TGR0B H'0450 H'0200 TGR0A H'0000 H'0200 TGR0C Transfer TGR0A TIOC0A H'0200 H'0450 H'0520 H'0450 Time H'0520
Figure 8.19 Buffer Operation Example (Output Compare Register) Buffer Operation Examples--when TGR Is an Input Capture Register: Figure 8.20 shows an example of TGRA set as an input capture register with the TGRA and TGRB registers set for buffer operation. The TCNT counter is cleared by a TGRA register input capture, and the TIOCA pin input capture input edge is selected as both rising and falling edge. Because buffer mode is selected, an input capture A causes the TCNT counter value to be stored in the TGRA register, and the value that was stored in the TGRA up until that time is simultaneously transferred to the TGRC register.
TCNT value H'0F07 H'09FB H'0532 H'0000 TIOC0A TGRA TGRC H'0532 H'0F07 H'0532 H'09FB H'0F07 Time
Figure 8.20 Buffer Operation Example (Input Capture Register)
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8.4.5
Cascade Connection Mode
Cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. This function operates by using the TPSC2 to TPSC0 bits of the TCR register to set the channel 1 counter clock to count by TCNT2 counter overflow. Table 8.6 shows the cascade connection combinations. Table 8.6 Cascade Connection Combinations
Upper 16 Bits TCNT1 Lower 16 Bits TCNT2
Combination Channel 1, channel 2
Procedure for Setting Cascade Connection Mode (Figure 8.21): 1. Set the TPSC2 to TPSC 0 bits of the channel 1 timer control register (TCR) to B'111 to select "count by TCNT2 overflow." 2. Set the CST bits corresponding to the upper and lower 16 bits in the TSTR to 1 to start the count operation.
Cascade connection operation Select cascade connection Start counting Cascade connection operation
(1)
(2)
Figure 8.21 Procedure for Selecting Cascade Connection Mode Cascade Connection Mode Examples--Input Capture: Figure 8.22 shows an example of operation when the TCNT1 counter is set to count on TCNT2 overflow, the TGR1A and TGR2A registers are set as input capture registers, and the TIOC pin rising edge is selected. Through simultaneous input of the rising edge to the TIOC1A and TIOC2A pins, 32-bit data is transferred, with the upper 16 bits to the TGR1A register and the lower 16 bits to the TGR2A register.
134
TCNT1 Clock TCNT1 TCNT2 Clock TCNT2 TIOC1A, TIOC2A TGR1A TGR2A H'03A2 H'0000 H'FFFF H'0000 H'0001 H'03A1 H'03A2
Figure 8.22 Cascade Connection Operation Example (Input Capture) 8.4.6 PWM Mode
PWM mode outputs the various PWM waveforms from output pins. Output levels of 0 output, 1 output, or toggle output can be selected as the output level for the compare-match of each TGR. A period can be set for a register by using the TGR compare-match as a counter clear source. All five channels can be independently set to PWM mode. Synchronous operation is also possible. There are two PWM modes: * PWM mode 1 Generates PWM output using the TGRA and TGRB registers, and TGRC and TGRD registers as pairs. The initial output values are those established in the TGRA and TGRC registers. When the values set in TGR registers being used as a pair are equal, output values will not change even if a compare-match occurs. A maximum of 4-phase PWM output is possible for PWM mode 1. * PWM mode 2 Generates PWM output using one TGR register as a period register and another as a duty cycle register. The output value of each pin upon a counter clear is the initial value established by the TIOR register. When the values set in the period register and duty register are equal, output values will not change even if a compare-match occurs.
135
Table 8.7 lists the combinations of PWM output pins and registers. Table 8.7 Combinations of PWM Output Pins and Registers
Output Pin Channel 0 (AB pair) 0 (CD pair) 1 2 Register TGR0A TGR0B TGR0C TGR0D TGR1A TGR1B TGR2A TGR2B PWM Mode 1 TIOC0A TIOC0C TIOC1A TIOC2A PWM Mode 2 TIOC 0A TIOC 0C TIOC 1A TIOC 1B TIOC 2A TIOC 2B
Note: PWM output of the period setting TGR is not possible in PWM mode 2.
Procedure for Selecting the PWM Mode (Figure 8.23): 1. Set bits TPSC2 to TPSC0 in the TCR to select the counter clock source. At the same time, set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock. 2. Set bits CCLR2 to CCLR0 in the TCR to select the TGR to be used as a counter clear source. 3. Set the period in the TGR selected in step 2, and the duty cycle in another TGR. 4. Using the timer I/O control register (TIOR), set the TGR selected in step 3 to act as an output compare register, and select the initial value and output value. 5. Set the MD3 to MD 0 bits in TMDR to select the PWM mode. 6. Set the CST bit in the TSTR to 1 to let the TCNT start counting.
136
PWM mode
Select counter clock
(1)
Select counter clear source
(2)
Select waveform output level
(3)
Set TGR
(4)
Select PWM mode
(5)
Start counting
(6)
PWM mode
Figure 8.23 Procedure for Selecting the PWM Mode PWM Mode Operation Examples--PWM Mode 1 (Figure 8.24): A TGRA register comparematch is used as a TCNT counter clear source, the TGRA register initial output value and output compare output value are both 0, and the TGRB register output compare output value is a 1. In this example, the value established in the TGRA register becomes the period and the value established in the TGRB register becomes the duty cycle.
TCNT value Counter cleared by TGRA compare match TGRA
TGRB H'0000 TIOCA Time
Figure 8.24 PWM Mode Operation Example (Mode 1)
137
PWM Mode Operation Examples--PWM Mode 2 (Figure 8.25): Channels 0 and 1 are set for synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source, the other TGR register initial output value is 0 and output compare output value is 1, and a 3-phase PWM waveform is output. In this example, the value established in the TGR1B register becomes the period and the value established in the other TGR register becomes the duty cycle.
TCNTvalue TGR1B TGR1A TGR0C TGR0A H'0000 TIOC0A Time
Counter cleared on TGR1B compare match
TIOC0C
TIOC1A
Figure 8.25 PWM Mode Operation Example (Mode 2) 0% Duty Cycle: Figure 8.26 shows an example of a 0% duty cycle PWM waveform output in PWM mode.
TCNT value TGRB rewrite TGRA TICCA
TGRB
TGRB rewrite
TGRB rewrite Time
0% duty cycle
Figure 8.26 PWM Mode Operation Example (0% Duty Cycle)
138
100% Duty Cycle: Figure 8.27 shows an example of a 100% duty cycle PWM waveform output in PWM mode. In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter.
TCNT value TGRA TGRB rewrite
Output does not change if period register and duty cycle register compare matches occur simultaneously
TGRB rewrite TGRB TGRB rewrite Time 100% duty cycle
TCNT value TGRB rewrite TGRA
Output does not change if period register and duty cycle register compare matches occur simultaneously
TGRB rewrite
TGRB TGRB rewrite
Time
100% duty cycle 0% duty cycle
Figure 8.27 PWM Mode Operation Example (100% Duty Cycle)
139
8.5
8.5.1
Interrupts
Interrupt Sources and Priority Ranking
The MTU has two interrupt sources: TGR register compare-match/input captures, TCNT counter overflows. Because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled. When an interrupt source is generated, the corresponding status flag in the timer status register (TSR) is set to 1. If the corresponding enable/disable bit in the timer input enable register (TIER) is set to 1 at this time, the MTU makes an interrupt request of the interrupt controller. The interrupt request is canceled by clearing the status flag to 0. The channel priority order can be changed with the interrupt controller. The priority ranking within a channel is fixed. For more information, see section 6, Interrupt Controller. Table 8.8 lists the MTU interrupt sources. Input Capture/Compare Match Interrupts: If the TGIE bit of the timer input enable register (TIER) is already set to 1 when the TGF flag in the timer status register (TSR) is set to 1 by a TGR register input capture/compare-match of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TGF flag to 0. The MTU has 8 input capture/compare-match interrupts; four each for channel 0, and two each for channels 1 and 2. Overflow Interrupts: If the TCIEV bit of the TIER is already set to 1 when the TCFV flag in the TSR is set to 1 by a TCNT counter overflow of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TCFV flag to 0. The MTU has three overflow interrupts, one for each channel.
140
Table 8.8
Channel 0
MTU Interrupt Sources
Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V Description TGR0A input capture/compare-match TGR0B input capture/compare-match TGR0C input capture/compare-match TGR0D input capture/compare-match TCNT0 overflow TGR1A input capture/compare-match TGR1B input capture/compare-match TCNT1 overflow TGR2A input capture/compare-match TGR2B input capture/compare-match TCNT2 overflow Low Priority* High
1
TGI1A TGI1B TCI1V
2
TGI2A TGI2B TCI2V
Note: * Indicates the initial status following reset. The ranking of channels can be altered using the interrupt controller.
8.5.2
A/D Converter Activation
The TGRA register input capture/compare-match of any channel can be used to activate the onchip A/D converter. If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to 1 by a TGRA register input capture/compare-match of any of the channels, an A/D conversion start request is sent to the A/D converter. If the MTU conversion start trigger is selected at such a time on the A/D converter side when this happens, the A/D conversion starts. The MTU has 3 TGRA register input capture/compare-match interrupts, one for each channel, that can be used as A/D converter activation sources.
141
8.6
8.6.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown in figure 8.28.
Internal clock TCNT input clock TCNT N-1 N N+1 N+2
Falling edge
Rising edge
Falling edge
Figure 8.28 TCNT Count Timing during Internal Clock Operation Output Compare Output Timing: The compare-match signal is generated at the final state of TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR or TOCR is output to the output compare output pin (TIOC pin). After TCNT and TGR matching, a compare-match signal is not issued until immediately before the TCNT input clock. Output compare output timing (normal mode and PWM mode) is shown in figure 8.29.
142
TCNT input clock
TCNT
N
N+1
TGR Comparematch signal TIOC pin
N
Figure 8.29 Output Compare Output Timing (Normal Mode/PWM Mode) Input Capture Signal Timing: Figure 8.30 illustrates input capture timing.
Input capture input Input capture signal TCNT N N+1 N+2
Rising edge
Falling edge
TGR
N
N+2
Figure 8.30 Input Capture Input Signal Timing
143
Counter Clearing Timing Due to Compare-Match/Input Capture: Timing for counter clearing due to compare-match is shown in figure 8.31. Figure 8.32 shows the timing for counter clearing due to input capture.
Comparematch signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 8.31 Counter Clearing Timing (Compare-Match)
Input capture signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 8.32 Counter Clearing Timing (Input Capture)
144
Buffer Operation Timing: Compare-match buffer operation timing is shown in figure 8.33. Figure 8.34 shows input capture buffer operation timing.
TCNT Comparematch signal Comparematch buffer signal TGRA, TGRB
n
n+1
n
N
TGRC, TGRD
N
Figure 8.33 Buffer Operation Timing (Compare-Match)
Input capture signal Input capture signal buffer N N+1
TCNT
TGRA, TGRB
n
N
N+1
TGRC, TGRD
n
N
Figure 8.34 Buffer Operation Timing (Input Capture)
145
8.6.2
Interrupt Signal Timing
Setting TGF Flag Timing during Compare-Match: Figure 8.35 shows timing for the TGF flag of the timer status register (TSR) due to compare-match, as well as TGI interrupt request signal timing.
TCNT input clock TCNT N N+1
TGR Comparematch signal TGF flag
N
TGI interrupt
Figure 8.35 TGI Interrupt Timing (Compare Match)
146
Setting TGF Flag Timing during Input Capture: Figure 8.36 shows timing for the TGF flag of the timer status register (TSR) due to input capture, as well as TGI interrupt request signal timing.
Input capture signal TCNT N
TGR
N
TGF flag
TGI interrupt
Figure 8.36 TGI Interrupt Timing (Input Capture) Setting Timing for Overflow Flag (TCFV): Figure 8.37 shows timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000
TCIV interrupt
Figure 8.37 TCIV Interrupt Setting Timing
147
Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. Figure 8.38 shows the timing for status flag clearing by the CPU.
TSR write cycle T1 Address T2
TSR address
Write signal
Status flag
Interrupt request signal
Figure 8.38 Timing of Status Flag Clearing by the CPU
8.7
Notes and Precautions
This section describes contention and other matters requiring special attention during MTU operations. Note on Cycle Setting: When setting a counter clearing by compare-match, clearing is done in the final state when TCNT matches the TGR value (update timing for count value on TCNT match). The actual number of states set in the counter is given by the following equation:
f= (N + 1)
(f: counter frequency, : operating frequency, N: value set in the TGR)
Contention between TCNT Write and Clear: If a counter clear signal is issued in the T 2 state during the TCNT write cycle, TCNT clearing has priority, and TCNT write is not conducted (figure 8.39).
148
TCNT write cycle T1 Address Write signal Counter clear signal TCNT N H'0000 TCNT address T2
Figure 8.39 TCNT Write and Clear Contention Contention between TCNT Write and Increment: If a count-up signal is issued in the T2 state during the TCNT write cycle, TCNT write has priority, and the counter is not incremented (figure 8.40).
TCNT write cycle T1 T2
Address
TCNT address
Write signal TCNT input clock TCNT N M
TCNT write data
Figure 8.40 TCNT Write and Increment Contention
149
Contention between Buffer Register Write and Compare Match: If a compare-match occurs in the T2 state of the TGR write cycle, data is transferred by the buffer operation from the buffer register to the TGR. On channel 0, the data to be transferred is that after the write (figure 8.41).
TGR write cycle T1 Buffer register address T2
Address Write signal Compare match signal Compare match buffer signal
Buffer register write data Buffer register TGR N M M
Figure 8.41 TGR Write and Compare-Match Contention (Channel 0)
150
Contention between TGR Read and Input Capture: If an input capture signal is issued in the T1 state of the TGR read cycle, the read data is that after input capture transfer (figure 8.42).
TGR read cycle T1 Address Read signal Input capture signal TGR X M TGR address T2
Internal data bus
M
Figure 8.42 TGR Read and Input Capture Contention
151
Contention between TGR Write and Input Capture: If an input capture signal is issued in the T2 state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure 8.43).
TGR write cycle T1 Address Write signal Input capture signal TCNT TGR M M TGR address T2
Figure 8.43 TGR Write and Input Capture Contention
152
Contention between Buffer Register Write and Input Capture: If an input capture signal is issued in the T 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 8.44).
Buffer register write cycle T1 Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address T2
Figure 8.44 Buffer Register Write and Input Capture Contention
153
Contention Between TGR Write and Compare Match: If a compare-match occurs in the T2 state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued (figure 8.45).
TGR write cycle T1 Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address T2
Figure 8.45 TGR Write and Compare Match Contention TCNT2 Write and Overflow Contention in Cascade Connection: With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT1 count (during a TCNT2 overflow) in the T 2 state of the TCNT2 write cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if there is match with TGR1A and the TCNT1 value, a compare signal is issued. When the TCNT1 count clock is selected as the channel 0 input capture source, TGR0A and TGR0C operate as input capture registers. When TGR0C comparematch/input capture is selected as the TGR1B input capture source, TGR1B operates as an input capture register. The timing is shown in figure 8.46. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.
154
TCNT write cycle T1 Address Write signal TCNT2 H'FFFE H'FFFF TCNT2 write data TGR2A to B Ch2 comparematch signal A/B TCNT1 input clock TCNT1 TGR1A Ch1 comparematch signal A TGR1B Ch1 inputcapture signal B TCNT0 P N M M M Disabled H'FFFF N N+1 T2
TCNT2 address
TGR0A to D Ch0 input capture signal A, C
Q
P
Figure 8.46 TCNT2 Write and Overflow Contention with Cascade Connection
155
Contention between Overflow and Counter Clearing: If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes precedence. Figure 8.47 shows the operation timing when a TGR compare-match is specified as the clearing source, and H'FFFF is set in TGR.
o
TCNT input clock TCNT
H'FFFF
H'0000
Counter clear signal
TGF flag Disabled TCFV flag
Figure 8.47 Contention between Overflow and Counter Clearing Contention between TCNT Write and Overflow: If there is an up-count in the T2 state of a TCNT write cycle, and overflow occurs, the TCNT write takes precedence and the TCFV flag in TSR is not set .
156
Figure 8.48 shows the operation timing in this case.
TCNT write cycle T1 o T2
Address
TCNT address
Write signal
TCNT input clock
TCNT
H'FFFF
N
TCNT write data
Disabled TCFV flag
Figure 8.48 Contention between TCNT Write and Overflow
8.8
8.8.1
MTU Output Pin Initialization
Operating Modes
The MTU has the following three operating modes. Waveform output is possible in all of these modes. * Normal mode (channels 0 to 2) * PWM mode 1 (channels 0 to 2) * PWM mode 2 (channels 0 to 2) The MTU output pin initialization method for each of these modes is described in this section.
157
8.8.2
Reset Start Operation
The MTU output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: * Represents the channel number and port symbol. 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc.
If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has three operating modes, as stated above. There are thus 9 mode transition combinations. Possible mode transition combinations are shown in table 8.9. Table 8.9 Mode Transition Combinations
After Before Normal PWM1 PWM2 Normal (1) (4) (7) PWM1 (2) (5) (8) PWM2 (3) (6) (9)
Legend: Normal: Normal mode PWM1: PWM1 mode PWM2: PWM2 mode The above abbreviations are used in some places in the following descriptions.
158
8.8.4
Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc.
* When making a transition to a mode (Normal, PWM1, PWM2) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. Note: An asterisk in this section represents the channel number. Pin initialization procedures are described below for the numbered combinations in table 8.9. The active level is assumed to be low.
159
(1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.49 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
1 2 RESET TMDR (normal) 5 3 4 TIOR PFC TSTR (1) (1 init (MTU) 0 out) 6 Match 13 12 11 10 9 8 7 PFC TSTR TMDR TIOR PFC TSTR Error (1) occurs (PORT) (0) (normal) (1 init (MTU) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z
Figure 8.49 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR.
10. Not necessary when restarting in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
160
(2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.50 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
1 2 RESET TMDR (normal) 5 3 4 TIOR PFC TSTR (1) (1 init (MTU) 0 out) 6 Match 13 12 11 10 9 8 7 PFC TSTR TMDR TIOR PFC TSTR Error (1) occurs (PORT) (0) (PWM1) (1 init (MTU) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (TO*B)
Figure 8.50 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.49. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TO*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
161
(3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 8.51 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
1 2 RESET TMDR (normal) 5 3 4 TIOR PFC TSTR (1) ("1"init (MTU) "0"out) 6 Match 13 12 11 10 9 8 7 PFC TSTR TMDR TIOR PFC TSTR Error (1) occurs (PORT) (0) (PWM2) (1 init (MTU) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (cycle register)
Figure 8.51 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.49. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
162
(4) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 8.52 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
1 2 RESET TMDR (PWM1) 5 3 4 TIOR PFC TSTR (1) (1 init (MTU) 0 out) 6 Match 13 12 11 10 9 8 7 PFC TSTR TMDR TIOR PFC TSTR Error (1) occurs (PORT) (0) (normal) (1 init (MTU) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z
* Not initialized (TIOC*B)
Figure 8.52 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 1. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
163
(5) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.53 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
1 2 RESET TMDR (PWM1) 5 3 4 TIOR PFC TSTR (1) (1 init (MTU) 0 out) 6 Match 13 12 11 10 9 8 7 PFC TSTR TMDR TIOR PFC TSTR Error (1) occurs (PORT) (0) (PWM1) (1 init (MTU) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (TIOC*B) * Not initialized (TIOC*B)
Figure 8.53 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.52. 10. Not necessary when restarting in PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
164
(6) Operation when Rrror Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.54 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
1 2 RESET TMDR (PWM1) 5 3 4 TIOR PFC TSTR (1) (1 init (MTU) 0 out) 6 Match 13 12 11 10 9 8 7 PFC TSTR TMDR TIOR PFC TSTR Error (1) occurs (PORT) (0) (PWM2) (1 init (MTU) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (TIOC*B) * Not initialized (cycle register)
Figure 8.54 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.52. 10. 11. 12. 13. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU output with the PFC. Operation is restarted by TSTR.
165
(7) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 8.55 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
3 1 2 RESET TMDR TIOR (PWM2) (1 init 0 out) 13 12 11 10 9 8 6 7 4 5 PFC TSTR TMDR TIOR PFC TSTR PFC TSTR Match Error (1) occurs (PORT) (0) (normal) (1 init (MTU) (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (cycle register)
Figure 8.55 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC*A is the cycle register.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR.
4. 5. 6. 7. 8. 9.
10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
166
(8) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.56 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
3 1 2 RESET TMDR TIOR (PWM2) (1 init 0 out) 13 12 11 10 9 8 6 7 4 5 PFC TSTR TMDR TIOR PFC TSTR PFC TSTR Match Error (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (cycle register) * Not initialized (TIOC*B)
Figure 8.56 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.55. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
167
(9) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.57 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
13 12 11 10 9 8 6 7 4 5 3 1 2 PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR PFC TSTR Match Error (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) (PWM2) (1 init (MTU) 0 out) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4 to 7, 12 to 14 Z Z * Not initialized (cycle register) * Not initialized (cycle register)
Figure 8.57 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.55. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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Section 9 8-Bit Timer 2 (TIM2)
9.1 Overview
8-bit timer 2 (TIM2) is a single-channel interval timer that generates compare match interrupts. 9.1.1 Features
* 8-bit interval timer * Generates compare match interrupts A compare match interrupt is generated by a counter compare match. * Selection of seven counter input clock sources
169
9.1.2
Block Diagram
Figure 9.1 shows a block diagram of 8-bit timer 2 (TIM2).
CMI (interrupt request signal)
Interrupt control Clock Clock selection
/2 /8 /32 /128 /512 /2048 /4096
T2COR
Comparator
T2CNT
T2CSR
Module bus
Bus interface
8-bit timer 2 T2CSR: Timer 2 control/status register T2CNT: Timer 2 counter T2COR: Timer 2 constant register
Figure 9.1 Block Diagram of 8-Bit Timer 2 9.1.3 Register Configuration
8-bit timer 2 (TIM2) has three registers for compare match cycle setting, clock selection, and other functions. The register configuration is shown in table 9.1. All the registers are 16 bits in size, and are initialized by a power-on reset.
170
Internal bus
Table 9.1
Name
8-Bit Timer 2 Registers
Abbreviation T2CSR T2CNT T2COR R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 Address H'FFFF862C H'FFFF862E H'FFFF8630 Access Size 8, 16, 32 8, 16, 32 8, 16
Timer 2 control/status register Timer 2 counter Timer 2 constant register
9.2
9.2.1
Register Descriptions
Timer 2 Control/Status Register (T2CSR)
The timer 2 control/status register (T2CSR) is a 16-bit readable/writable* register that selects the clock to be input to the timer 2 counter (T2CNT) and controls compare match interrupts (CMI). T2CSR is initialized to H'0000 by a power-on reset.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 CMF 0 R/W 13 -- 0 R 5 CMIE 0 R/W 12 -- 0 R 4 CKS2 0 R/W 11 -- 0 R 3 CKS1 0 R/W 10 -- 0 R 2 CKS0 0 R/W 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 -- 0 R
* Bits 15 to 7--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 6--Compare Match Flag (CMF): Status flag that indicates a match between the values of T2CNT and T2COR. The setting and clearing conditions for this flag are shown below.
Bit 6: CMF 0 1 Description [Clearing condition] Cleared by reading T2CSR when CMF = 1, then writing 0 in CMF (Initial value) [Setting condition] Set when T2CNT = T2COR*
Note: * When T2CNT and T2COR still contain their initial values (when the initial values have not been changed or when the T2CNT value has not been incremented), CMF is not set even though the T2CNT and T2COR values are the same (H'0000). 171
* Bit 5--Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests initiated by the CMF flag when set to 1 in T2CSR.
Bit 5: CMIE 0 1 Description Interrupt request by CMF flag disabled Interrupt request by CMF flag enabled (Initial value)
* Bits 4 to 2--Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of seven internal clock sources, obtained by dividing the system clock (), for input to T2CNT.
Bit 4: CKS2 0 Bit 3: CKS1 0 Bit 2: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Up-count stopped /2 /8 /32 /128 /512 /2048 /4096 (Initial value)
* Bits 1 and 0--Reserved: These bits are always read as 0. The write value should always be 0. 9.2.2 Timer 2 Counter (T2CNT)
The timer 2 counter (T2CNT) is a 16-bit readable/writable register used as an 8-bit up-counter. T2CNT increments on the internal clock selected by bits CKS2 to CKS0 in T2CSR. The T2CNT value can be read or written by the CPU at all times. When the T2CNT value matches the value in the timer 2 constant register (T2COR), T2CNT is cleared to H'0000 and the CMF flag is set to 1 in T2CSR. If the CMIE bit in T2CSR is set to 1 at this time, a compare match interrupt (CMI) is generated. Bits 15 to 8 are reserved and have no counter function. These bits are always read as 0. The write value should always be 0. T2CNT is initialized to H'0000 by a power-on reset.
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Bit:
15 --
14 -- 0 R 6
13 -- 0 R 5
12 -- 0 R 4
11 -- 0 R 3
10 -- 0 R 2
9 -- 0 R 1
8 -- 0 R 0
Initial value: R/W: Bit:
0 R 7
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
9.2.3
Timer 2 Constant Register (T2COR)
The timer 2 constant register (T2COR) is a 16-bit readable/writable register that is used to set the T2CNT compare match cycle. The values in T2COR and T2CNT are continually compared, and when the values match the CMF flag is set in T2CSR and T2CNT is cleared to 0. If the CMIE bit in T2CSR is set to 1, an interrupt request is sent to the interrupt controller in response to the match signal. The interrupt request is output continuously until the CMF flag in T2CSR is cleared. Bits 15 to 8 are reserved and are not used in the cycle setting. These bits are always read as 0. The write value should always be 0. T2COR is initialized to H'0000 by a power-on reset.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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9.3
9.3.1
Operation
Cyclic Count Operation
When a clock is selected with bits CKS2 to CKS0 in the T2CSR register, the T2CNT counter starts incrementing on the selected clock. When the T2CNT counter value matches the value in the timer 2 constant register (T2COR), the T2CNT counter is cleared to H'00, and the CMF flag is set to 1 in the T2CSR register. If the CMIE bit in T2CSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The T2CNT counter then starts incrementing again from H'00. The compare match counter operation is shown in figure 9.2.
T2CNT value Counter cleared by T2COR compare match T2COR
H'00
Time
Figure 9.2 Counter Operation 9.3.2 T2CNT Count Timing
Any of seven internal clocks (/2, /8, /32, /128, /512, /2048, or /4096) divided from the system clock (CK) can be selected with bits CKS2 to CKS0 in T2CSR. The count timing is shown in figure 9.3.
CK Internal clock T2CNT input clock T2CNT N-1 N N+1
Figure 9.3 Count Timing
174
9.4
9.4.1
Interrupts
Interrupt Source
When interrupt request flag CMF is set to 1, and interrupt enable bit CMIE is also 1, the corresponding interrupt request is output. 9.4.2 Timing of Compare Match Flag Setting
The CMF bit in the T2CSR register is set to 1 by the compare match signal generated when the T2COR register and T2CNT counter values match. The compare match signal is generated in the last state in which the match is true (when the value at which the T2CNT counter match occurred is about to be updated). Therefore, after a match between the T2CNT counter and the T2COR register, the compare match signal is not generated until the next T2CNT counter input clock pulse. Figure 9.4 shows the timing of CMF bit setting.
CK T2CNT input clock pulse T2CNT T2COR Compare match signal CMF CMI N N 0
Figure 9.4 Timing of CMF Setting
175
9.4.3
Timing of Compare Match Flag Clearing
The CMF bit in the T2CSR register is cleared by reading the bit when it is set to 1, then writing 0 in it. Figure 9.5 shows the timing of CMF bit clearing by the CPU.
T2CSR write cycle T1 CK CMF T2
Figure 9.5 Timing of CMF Clearing by CPU
176
Section 10 Compare Match Timer (CMT)
10.1 Overview
The SH7018 has an on-chip compare match timer (CMT) configured of 16-bit timers for two channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 10.1.1 Features
The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (/8, /32, /128, /512) can be selected independently for each channel. * Interrupt sources A compare match interrupt can be requested independently for each channel.
177
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of the CMT.
CMI0 /8 /32 /128 /512 CMI1 /8 /32 /128 /512
Control circuit
Clock selection
Control circuit
Clock selection
Comparator
Comparator
CMCOR0
CMCOR1
CMCSR0
CMCSR1
CMCNT0
CMCNT1 Bus interface Internal bus
CMSTR
Module bus CMT CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt
Figure 10.1 CMT Block Diagram
178
10.1.3
Register Configuration
Table 10.1 summarizes the CMT register configuration. Table 10.1 Register Configuration
Channel Name Shared 0 Abbreviation R/W R/W R/(W)* R/W R/W R/(W)* R/W R/W Initial Value H'0000 H'0000 H'0000 Address Access Size (Bits)
Compare match timer CMSTR start register Compare match timer CMCSR0 control/status register 0 Compare match timer CMCNT0 counter 0 Compare match timer CMCOR0 constant register 0
H'FFFF83D0 8, 16, 32 H'FFFF83D2 8, 16, 32 H'FFFF83D4 8, 16, 32
H'FFFF H'FFFF83D6 8, 16, 32 H'0000 H'0000 H'FFFF83D8 8, 16, 32 H'FFFF83DA 8, 16, 32
1
Compare match timer CMCSR1 control/status register 1 Compare match timer CMCNT1 counter 1 Compare match timer CMCOR1 constant register 1
H'FFFF H'FFFF83DC 8, 16
Note: * The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to clear the flags.
179
10.2
10.2.1
Register Descriptions
Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by power-on resets.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 STR1 0 R/W 8 -- 0 R 0 STR0 0 R/W
* Bits 15 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1 (CMCNT1).
Bit 1: STR1 0 1 Description CMCNT1 count operation halted CMCNT1 count operation (Initial value)
* Bit 0--Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0 (CMCNT0).
Bit 0: STR0 0 1 Description CMCNT0 count operation halted CMCNT0 count operation (Initial value)
180
10.2.2
Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by power-on resets.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 CMF Initial value: R/W: 0 R/(W)* 14 -- 0 R 6 CMIE 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKS1 0 R/W 8 -- 0 R 0 CKS0 0 R/W
Note: * The only value that can be written is a 0 to clear the flag.
* Bits 15 to 8 and 5 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 7--Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched.
Bit 7: CMF 0 Description CMCNT and CMCOR values have not matched Clear condition: Write a 0 to CMF after reading a 1 from it 1 CMCNT and CMCOR values have matched (Initial value)
* Bit 6--Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1).
Bit 6: CMIE 0 1 Description Compare match interrupts (CMI) disabled Compare match interrupts (CMI) enabled (Initial value)
181
* Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock (). When the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and CKS0.
Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description /8 /32 /128 /512 (Initial value)
10.2.3
Compare Match Timer Counter (CMCNT)
The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for generating interrupt requests. When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), the CMCNT is cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT is initialized to H'0000 by power-on resets.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
182
10.2.4
Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by power-on resets.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
10.3
10.3.1
Operation
Period Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 10.2 shows the compare match counter operation.
CMCNT value CMCOR
Counter cleared by CMCOR compare match
H'0000
Time
Figure 10.2 Counter Operation
183
10.3.2
CMCNT Count Timing
One of four clocks (/8, /32, /128, /512) obtained by dividing the system clock (CK) can be selected by the CKS1 and CKS0 bits of the CMCSR. Figure 10.3 shows the timing.
CK Internal clock CMCNT input clock CMCNT N-1 N N+1
Figure 10.3 Count Timing
10.4
10.4.1
Interrupts
Interrupt Sources
The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when the interrupt request flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details. 10.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 10.4 shows the CMF bit set timing.
184
CK
CMCNT input clock
CMCNT
N
0
CMCOR
N
Compare match signal
CMF
CMI
Figure 10.4 CMF Set Timing 10.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1. Figure 10.5 shows the timing when the CMF bit is cleared by the CPU.
CMCSR write cycle T1 CK T2
CMF
Figure 10.5 Timing of CMF Clear by the CPU
185
10.5
Notes on Use
Take care that the contentions described in sections 10.5.1 to 10.5.3 do not arise during CMT operation. 10.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 10.6 shows the timing.
CMCNT write cycle T1 T2
CK
Address
CMCNT
Internal write signal Compare match signal
CMCNT
N
H'0000
Figure 10.6 CMCNT Write and Compare Match Contention
186
10.5.2
Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T 2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 10.7 shows the timing.
CMCNT write cycle T1 T2
CK
Address
CMCNT
Internal write signal Compare match signal
CMCNT
N
M CMCNT write data
Figure 10.7 CMCNT Word Write and Increment Contention
187
10.5.3
Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T 2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write. Figure 10.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle.
CMCNT write cycle T1 CK T2
Address
CMCNTH
Internal write signal CMCNT input clock
CMCNTH
N
M CMCNTH write data
CMCNTL
X
X
Figure 10.8 CMCNT Byte Write and Increment Contention
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Section 11 Watchdog Timer (WDT)
11.1 Overview
The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If the WDT overflows without being rewritten correctly by the CPU due to system runaway or the like, it can generate an internal reset signal for the chip. When the watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used in recovering from the standby mode. 11.1.1 Features
* Works in watchdog timer mode or interval timer mode. * If the counter overflows in the watchdog timer mode, WDT can generate an internal reset signal for the chip. * Generates interrupts in the interval timer mode. When the counter overflows, it generates an interval timer interrupt. * Clears standby mode. * Works with eight counter input clocks.
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11.1.2
Block Diagram
Figure 11.1 is the block diagram of the WDT.
ITI (interrupt signal)
Overflow Interrupt control Clock Clock select
Internal reset signal*
Reset control
/2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources Internal data bus
RSTCSR
TCNT
TCSR
Module bus WDT TCSR: TCNT: RSTCSR: Note: *
Bus interface
Timer control/status register Timer counter Reset control/status register The internal reset signal can be generated by setting the register.
Figure 11.1 WDT Block Diagram
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11.1.3
Register Configuration
Table 11.1 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 11.1 WDT Registers
Address Name Timer control/status register Timer counter Reset control/status register Abbreviation R/W TCSR TCNT RSTCSR R/(W)*3 R/W R/(W)*
3
Initial Value H'18 H'00 H'1F
Write*
1
Read* 2 H'FFFF8610 H'FFFF8611
H'FFFF8610
H'FFFF8612
H'FFFF8613
Notes: 1. Write by word transfer. It cannot be written in byte or longword. 2. Read by byte transfer. It cannot be read in word or longword. 3. Only 0 can be written in bit 7 to clear the flag.
11.2
11.2.1
Register Descriptions
Timer Counter (TCNT)
The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), an internal reset signal from the watchdog timer* or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of the TCSR. The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not initialized in the standby mode. Note: * If RSTE of RSTCSR is set to 1.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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11.2.2
Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for details.) Its functions include selecting the clock input source and mode of the timer counter (TCNT). Bits 7 to 5 are initialized to 000 by a power-on reset or in standby mode. Bits 2 to 0 are initialized to 000 by a power-on reset, but retain their values in the standby mode.
Bit: 7 OVF Initial value: R/W: 0 R/(W) 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 R 3 -- 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
* Bit 7--Overflow Flag (OVF): Indicates that the TCNT has overflowed from H'FF to H'00 in the interval timer mode. It is not set in the watchdog timer mode.
Bit 7: OVF 0 Description No overflow of TCNT in interval timer mode Cleared by reading OVF, then writing 0 in OVF 1 TCNT overflow in the interval timer mode (Initial value)
* Bit 6--Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer.
Bit 6: WT/IT 0 1 Description Interval timer mode (Initial value)
Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. (Section 11.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in the watchdog timer mode.)
* Bit 5--Timer Enable (TME): Enables or disables the timer.
Bit 5: TME 0 1 Description Timer disabled: TCNT is initialized to H'00 and count-up stops (Initial value) Timer enabled: TCNT starts counting.
* Bits 4 and 3--Reserved: These bits are always read as 1. The write value should always be 1.
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* Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the system clock ().
Description Bit 2: CKS2 Bit 1: CKS1 0 0 Bit 0: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Source /2 (Initial value) /64 /128 /256 /512 /1024 /4096 /8192 Overflow Interval* ( = 20.0 MHz) 25.6 s 819.2 s 1.6384 ms 3.2768 ms 6.5536 ms 13.1072 ms 52.4288 ms 104.8576 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs.
11.2.3
Reset Control/Status Register (RSTCSR)
The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers in that it is more difficult to write. See section 11.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow and selects the internal reset signal type. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is initialized to H'1F in standby mode.
Bit: 7 WOVF Initial value: R/W: Note: * 0 R/(W)* 6 RSTE 0 R/W 5 -- 0 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R
Only 0 can be written in bit 7 to clear the flag.
* Bit 7--Watchdog Timer Overflow Flag (WOVF): Indicates that the TCNT has overflowed (H'FF to H'00) in the watchdog timer mode. It is not set in the interval timer mode.
193
Bit 7: WOVF 0
Description No TCNT overflow in watchdog timer mode (Initial value)
Cleared when software reads WOVF, then writes 0 in WOVF 1 Set by TCNT overflow in watchdog timer mode
* Bit 6--Reset Enable (RSTE): Selects whether to reset the chip internally if the TCNT overflows in the watchdog timer mode.
Bit 6: RSTE 0 Description Not reset when TCNT overflows (Initial value)
LSI not reset internally, but TCNT and TCSR reset within WDT. 1 Reset when TCNT overflows
* Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 4 to 0--Reserved: These bits are always read as 1. The write value should always be 1. 11.2.4 Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. The TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the TCSR) (figure 11.2). This transfers the write data from the lower byte to the TCNT or TCSR.
Writing to the TCNT 15 Address: H'FFFF8610 H'5A 8 7 Write data 0
Writing to the TCSR 15 Address: H'FFFF8610 H'A5 8 7 Write data 0
Figure 11.2 Writing to the TCNT and TCSR
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Writing to the RSTCSR: The RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 11.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit 15 Address: H'FFFF8612 H'A5 8 7 H'00 0
Writing to the RSTE and RSTS bits 15 Address: H'FFFF8612 H'5A 8 7 Write data 0
Figure 11.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR, H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR.
11.3
11.3.1
Operation
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if RSTE of RSTCSR is set to 1 and a problem such as system runaway occurs, the value of TCNT is not overwritten and an overflow results. This causes WDT to generate an internal reset signal for the chip. The internal reset signal is output for 512 clock cycles. Figure 11.4 shows the timing. When a watchdog overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit is cleared to 0. The following are not initialized a WDT reset signal:
195
* PFC (Pin Function Controller) function register * I/O port register Initializing is only possible by external power-on reset.
TCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1
Time WT/IT = 1 H'00 written TME = 1 in TCNT
Internal reset generated Internal reset signal* WT/IT: Timer mode select bit TME: Timer enable bit 512 clocks
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 11.4 Operation in the Watchdog Timer Mode
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11.3.2
Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 11.5).
TCNT value H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI
Time
ITI: Interval timer interrupt request generation
Figure 11.5 Operation in the Interval Timer Mode 11.3.3 Clearing the Standby Mode
The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When using the standby mode, set the WDT as described below. Before Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 19.3, AC Characteristics, for the oscillation settling time. Recovery from the Standby Mode: When an NMI request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected by bits CKS2 to CKS0 before the standby mode was entered. When the TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. For details on the standby mode, see section 18, Power Down State.
197
11.3.4
Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and an interval timer interrupt is simultaneously requested (figure 11.6).
CK
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 11.6 Timing of Setting the OVF 11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
If the timer counter (TCNT) overflows in the watchdog timer mode, the WOVF bit of the reset control/status register (RSTCSR) is set to 1. If the RSTE bit of RSTCSR is set to 1, an internal reset for the entire chip is generated when TCNT overflows. Figure 11.7 shows the timing.
CK
TCNT
H'FF
H'00
Overflow signal (internal signal)
WOVF
Figure 11.7 Timing of Setting the WOVF Bit
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11.4
11.4.1
Notes on Use
TCNT Write and Increment Contention
If a timer counter (TCNT) increment clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 11.8).
TCNT write cycle T1 CK Address Internal write signal TCNT input clock TCNT N M Counter write data TCNT address T2 T3
Figure 11.8 Contention between TCNT Write and Increment 11.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 11.4.3 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. 11.4.4 Internal Reset With the Watchdog Timer
If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a TCNT overflow occurs, but the TCNT and TCSR in the WDT will reset.
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200
Section 12 Serial Communication Interface (SCI1)
12.1 Overview
The SH7018 has a serial communication interface (SCI1) with one channel. The SCI supports asynchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 Features
* Select asynchronous or clock synchronous as the serial communications mode. Asynchronous mode: Serial data communications are synched by start-stop in character units. The SCI1 can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs a standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. Data length: seven or eight bits Stop bit length: one or two bits Parity: even, odd, or none Multiprocessor bit: one or none Receive error detection: parity, overrun, and framing errors Break detection: by reading the RxD level directly when a framing error occurs Clock synchronous mode: Serial data transfer is synchronized with the clock. This permits serial data communications with other LSI devices equipped with a clock synchronous communications function. One serial data communications format is supported. Number of data bits: 8 Receive error detection: Over-line error detection * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates. * Internal transmit/receive clock source: baud rate generator (internal). * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently.
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12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the SCI1.
Bus interface
Module data bus
Internal data bus
RDR1
TDR1
SSR1 SCR1
BRR1 /4 /16 /64
RxD
RSR1
TSR1
SMR1 Transmit/ receive control
Baud rate generator
TxD Parity generation Parity check SCK
Clock External clock TEI TxI RxI ERI SCI1
RSR1 : RDR1 : TSR1 : TDR1 :
Receive shift register Receive data register Transmit shift register Transmit data register
SMR1 : SCR1 : SSR1 : BRR1 :
Serial mode register Serial control register Serial status register Bit rate register
Figure 12.1 SCI1 Block Diagram 12.1.3 Pin Configuration
Table 12.1 summarizes the SCI1 pins by channel. Table 12.1 SCI1 Pins
Pin Name Serial clock pin Receive data pin Transmit data pin 202 Abbreviation SCK RxD TxD Input/Output Input/output Input Output Function SCI1 clock input/output SCI1 receive data input SCI1 transmit data output
12.1.4
Register Configuration
Table 12.2 summarizes the SCI1 internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 12.2 Registers
Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Abbreviation SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 R/W R/W R/W R/W R/W R/(W)* R
2
Initial Value H'00 H'FF H'00 H'FF H'84 H'00
Address* 1 H'FFFF81B0 H'FFFF81B1 H'FFFF81B2 H'FFFF81B3 H'FFFF81B4 H'FFFF81B5
Access Size 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16
Notes: 1. Do not attempt to access empty addresses. 2. The only value that can be written is a 0 to clear the flags.
12.2
12.2.1
Register Descriptions
Receive Shift Register (RSR1)
The receive shift register (RSR1) receives serial data. Data input at the RxD pin is loaded into the RSR1 in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the RDR1. The CPU cannot read or write the RSR1 directly.
Bit: 7 6 5 4 3 2 1 0
R/W:
--
--
--
--
--
--
--
--
12.2.2
Receive Data Register (RDR1)
The receive data register (RDR1) stores serial receive data. The SCI1 completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR1) into the RDR1 for storage. The RSR1 is then ready to receive the next data. This double buffering allows the SCI1 to receive data continuously. The CPU can read but not write the RDR1. The RDR is initialized to H'00 by a power-on reset or in standby mode.
203
Bit:
7
6
5
4
3
2
1
0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
12.2.3
Transmit Shift Register (TSR1)
The transmit shift register (TSR1) transmits serial data. The SCI1 loads transmit data from the transmit data register (TDR1) into the TSR1, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI1 automatically loads the next transmit data from the TDR1 into the TSR1 and starts transmitting again. If the TDRE bit of the SSR1 is 1, however, the SCI1 does not load the TDR1 contents into the TSR1. The CPU cannot read or write the TSR1 directly.
Bit: 7 6 5 4 3 2 1 0
R/W:
--
--
--
--
--
--
--
--
12.2.4
Transmit Data Register (TDR1)
The transmit data register (TDR1) is an 8-bit register that stores data for serial transmission. When the SCI1 detects that the transmit shift register (TSR1) is empty, it moves transmit data written in the TDR1 into the TSR1 and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the TDR1 during serial transmission from the TSR1. The CPU can always read and write the TDR1. The TDR1 is initialized to H'FF by a power-on reset or in standby mode.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
12.2.5
Serial Mode Register (SMR1)
The serial mode register (SMR1) is an 8-bit register that specifies the SCI1 serial communication format and selects the clock source for the baud rate generator.
204
The CPU can always read and write the SMR1. The SMR1 is initialized to H'00 by a power-on reset.
Bit: 7 C/A Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
* Bit 7--Communication Mode (C/A): Sets the SCI operation mode to either start-stop synchronous mode or clock synchronous mode.
Bit 7: C/A 0 1 Description Start-stop synchronous mode Clock synchronous mode (Initial value)
* Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. The number of data bits is fixed at eight in the clock synchronous mode, regardless of the CHR setting.
Bit 6: CHR 0 1 Description Eight-bit data Seven-bit data When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. (Initial value)
* Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data. A parity bit is added in the clock synchronous mode regardless of the setting of the PE bit, and no checking is performed.
Bit 5: PE 0 1 Description Parity bit not added or checked Parity bit added and checked When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. (Initial value)
* Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored when parity addition and check is disabled.
205
Bit 4: O/E 0
Description Even parity (Initial value)
If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.
* Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
Bit 3: STOP 0 Description One stop bit (Initial value)
In transmitting, a single bit of 1 is added at the end of each transmitted character. 1 Two stop bits In transmitting, two bits of 1 are added at the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, is it treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next character to be transmitted. * Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. Also, the setting of the MP bit is valid only in the start-stop synchronous mode. The setting of the MP bit is ignored in the clock synchronous mode. For the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication.
Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value)
* Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available; , /4, /16, or /64. For
206
further information on the clock source, bit rate register settings, and baud rate, see section 12.2.8, Bit Rate Register.
Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description /4 /16 /64 (Initial value)
12.2.6
Serial Control Register (SCR1)
The serial control register (SCR1) operates the SCI1 transmitter/receiver, enables/disables interrupt requests. The CPU can always read and write the SCR1. The SCR1 is initialized to H'00 by a power-on reset.
Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
* Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TxI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR1) is set to 1 by transfer of serial transmit data from the TDR1 to the TSR1.
Bit 7: TIE 0 Description Transmit-data-empty interrupt request (TxI) is disabled (Initial value)
The TxI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TxI) is enabled
* Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RxI) requested when the receive data register full bit (RDRF) in the serial status register (SSR1) is set to 1 by transfer of serial receive data from the RSR1 to the RDR1. It also enables or disables receive-error interrupt (ERI) requests.
207
Bit 6: RIE 0
Description Receive-data-full interrupt (RxI) and receive-error interrupt (ERI) requests are disabled. (Initial value) RxI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0.
1
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI) requests are enabled.
* Bit 5--Transmit Enable (TE): Enables or disables the SCI1 serial transmitter.
Bit 5: TE 0 Description Transmitter disabled (Initial value)
The transmit data register empty bit (TDRE) in the serial status register (SSR1) is locked at 1. 1 Transmitter enabled Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR1) is cleared to 0 after writing of transmit data into the TDR1. Select the transmit format in the SMR1 before setting TE to 1.
* Bit 4--Receive Enable (RE): Enables or disables the SCI1 serial receiver.
Bit 4: RE 0 Description Receiver disabled (Initial value)
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. Select the receive format in the SMR1 before setting RE to 1.
* Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only if the multiprocessor mode bit (MP) in the serial mode register (SMR1) is set to 1 during reception.
208
Bit 3: MPIE 0
Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) MPIE is cleared when the MPIE bit is cleared to 0, or the multiprocessor bit (MPB) is set to 1 in receive data.
1
Multiprocessor interrupts are enabled Receive-data-full interrupt requests (RxI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR1) are disabled until data with the multiprocessor bit set to 1 is received. The SCI does not transfer receive data from the RSR1 to the RDR1, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR1). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI1 automatically clears MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE bits in the SCR1 are set to 1), and allows the FER and ORER bits to be set.
* Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled* Transmit-end interrupt (TEI) requests are enabled.* (Initial value)
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR1) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0.
* Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI1 clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC). The CKE0 setting is valid only in the asynchronous mode, and only when the SCI1 is internally clocked (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI1 operating mode in the serial mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI1 clock source, see table 12.9 in section 12.3, Operation.
209
Bit 1: Bit 0: CKE1 CKE0 Description*1 0 0 Asynchronous mode Clock synchronous mode 0 1 Asynchronous mode Clock synchronous mode 1 0 Asynchronous mode Clock synchronous mode 1 1 Asynchronous mode Clock synchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined)* 2 Internal clock, SCK pin used for synchronous clock output* 2 Internal clock, SCK pin used for clock output* 3 Internal clock, SCK pin used for synchronous clock output External clock, SCK pin used for clock input* 4 External clock, SCK pin used for synchronous clock input External clock, SCK pin used for clock input* 4 External clock, SCK pin used for synchronous clock input
Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. 2. Initial value. 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate.
12.2.7
Serial Status Register (SSR1)
The serial status register (SSR1) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI1 operating status. The CPU can always read and write the SSR1, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR1 is initialized to H'84 by a power-on reset or in standby mode.
Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Note: * The only value that can be written is a 0 to clear the flag.
* Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI1 has loaded transmit data from the TDR1 into the TSR1 and new serial transmit data can be written in the TDR1.
210
Bit 7: TDRE 0
Description TDR1 contains valid transmit data TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE.
1
TDR1 does not contain valid transmit data
(Initial value)
TDRE is set to 1 when the chip is power-on reset or in standby mode, the TE bit in the serial control register (SCR1) is cleared to 0, or TDR1 contents are loaded into TSR1, so new data can be written in TDR1.
* Bit 6--Receive Data Register Full (RDRF): Indicates that RDR1 contains received data.
Bit 6: RDRF 0 Description RDR1 does not contain valid received data (Initial value)
RDRF is cleared to 0 when the chip is power-on reset or in standby mode, software reads RDRF after it has been set to 1, then writes 0 in RDRF. 1 RDR1 contains valid received data RDRF is set to 1 when serial data is received normally and transferred from RSR1 to RDR1. Note: The RDR1 and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register (SCR1). They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost.
* Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error.
Bit 5: ORER 0 Description Receiving is in progress or has ended normally (Initial value)
Clearing the RE bit to 0 in the serial control register (SCR1) does not affect the ORER bit, which retains its previous value. ORER is cleared to 0 when the chip is power-on reset, in standby mode, or software reads ORER after it has been set to 1, then writes 0 in ORER. 1 A receive overrun error occurred RDR1 continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.
211
* Bit 4--Framing Error (FER): Indicates that data reception ended abnormally due to a framing error.
Bit 4: FER 0 Description Receiving is in progress or has ended normally (Initial value)
Clearing the RE bit to 0 in the serial control register (SCR1) does not affect the FER bit, which retains its previous value. FER is cleared to 0 when the chip is power-on reset, in standby mode, or software reads FER after it has been set to 1, then writes 0 in FER. 1 A receive framing error occurred When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI1 transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0.
* Bit 3--Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error.
Bit 3: PER 0 Description Receiving is in progress or has ended normally (Initial value)
Clearing the RE bit to 0 in the serial control register (SCR1) does not affect the PER bit, which retains its previous value. PER is cleared to 0 when the chip is power-on reset, in standby mode, or software reads PER after it has been set to 1, then writes 0 in PER. 1 A receive parity error occurred When a parity error occurs, the SCI1 transfers the receive data into the RDR1 but does not set RDRF. Serial receiving cannot continue while PER is set to 1. PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR1).
212
* Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the TDR1 did not contain valid data, so transmission has ended. TEND is a readonly bit and cannot be written.
Bit 2: TEND 0 Description Transmission is in progress TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE. 1 End of transmission (Initial value)
TEND is set to 1 when the chip is power-on reset or in standby mode, TE is cleared to 0 in the serial control register (SCR1), or TDRE is 1 when the last bit of a one-byte serial character is transmitted.
* Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving. The MPB is a read-only bit and cannot be written.
Bit 1: MPB 0 Description Multiprocessor bit value in receive data is 0 (Initial value)
If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. 1 Multiprocessor bit value in receive data is 1
* Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting. The setting of the MPBT bit is ignored in the clock synchronous mode, when the multiprocessor format is not being used, and when transmission is not taking place.
Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value)
213
12.2.8
Bit Rate Register (BRR1)
The bit rate register (BRR1) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR1), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR1. The BRR1 is initialized to H'FF by a power-on reset.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Table 12.3 lists examples of BRR1 settings in the asynchronous mode. Table 12.4 lists examples of BRR1 settings in the clock synchronous mode. Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 4 n 2 1 1 0 0 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 8 6 3 3 2 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -3.55 -6.99 8.51 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 10 7 4 4 3 4.9152 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -3.03 0.00 6.67 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 12 9 6 5 4 6 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 -2.34 -6.99 0.00 -2.34
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Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode) (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 7.3728 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 15 11 7 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 16 12 8 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 2.12 0.16 -3.55 0.00 -6.99 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 20 15 10 9 7 9.8304 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.59 0.00 -3.03 -1.70 0.00
215
Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode) (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 10 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 21 15 10 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 -1.36 1.73 -1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 195 143 71 143 71 143 71 35 23 17 11 10 8 11.0592 Error (%) 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 25 19 12 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 0.00 -2.34
216
Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode) (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 26 19 12 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.23 0.00 2.56 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 29 22 14 13 10 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 1.27 -0.93 1.27 0.00 3.57 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 31 23 15 14 11 14.7456 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
217
Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode) (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 34 25 16 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.79 0.16 2.12 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 36 27 18 16 13 17.2032 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.90 0.00 -1.75 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 38 28 19 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 0.16 1.02 -2.34 0.00 -2.34
218
Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode) (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 18.432 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 81 239 119 239 119 239 119 59 39 29 19 17 14 Error (%) -0.22 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 42 31 20 19 15 19.6608 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -0.78 0.00 1.59 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 42 32 21 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.94 -1.36 -1.36 0.00 1.73
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Table 12.4 Bit Rates and BRR Settings in Clocked Synchronous Mode
(MHz) Bit Rate (Bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 4 n 3 2 2 1 1 0 0 0 0 0 0 0 N 141 249 124 249 99 199 99 39 19 9 3 1 n 3 3 2 2 1 1 0 0 0 0 0 0 0 8 N 212 124 249 124 199 99 199 79 39 19 7 3 1 n 3 3 3 2 1 1 0 0 0 0 0 0 -- 0 10 N 212 155 77 155 249 124 249 99 49 24 9 4 -- 0* n 3 3 3 2 2 1 1 0 0 0 0 0 0 0 12 N 212 187 93 187 74 149 74 119 59 29 11 5 2 0*
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Table 12.4 Bit Rates and BRR Settings in Clocked Synchronous Mode (cont)
(MHz) Bit Rate (Bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 16 n 3 3 3 2 2 1 1 0 0 0 0 0 0 -- N 212 249 124 249 99 199 99 159 79 39 15 7 3 -- n 3 3 3 3 2 1 1 0 0 0 0 0 0 0 0 20 N 212 249 155 77 124 249 124 199 99 49 19 9 4 1 0*
Note: Settings with an error of 1% or less are recommended. Legend Blank: No setting available --: Setting possible, but error occurs *: Continuous transmission/reception is not possible.
221
The BRR1 setting is calculated as follows: Asynchronous mode:
N=
64 x 22n-1 xB
x 106 - 1
Clock synchronous mode:
N=
8x 22n-1 xB
x 106 - 1
B: Bit rate (bit/s) N: Baud rate generator BRR1 setting (0 N 255)
: Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.)
SMR1 Settings n 0 1 2 3 Clock Source CKS1 0 0 1 1 CKS2 0 1 0 1
/4 /16 /64
The bit rate error in asynchronous mode is calculated as follows:
x 106 Error (%) = - 1 x 100 (N + 1) x B x 64 x 22n-1
222
Table 12.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used for various frequencies. Tables 12.6 and 12.7 show the maximum rates for external clock input.. Table 12.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
Settings (MHz) 4 4.9152 6 7.3728 8 9.8304 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 Maximum Bit Rate (Bits/s) 125000 153600 187500 230400 250000 307200 312500 345600 375000 384000 437500 460800 500000 537600 562500 576000 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
223
Table 12.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
(MHz) 4 4.9152 6 7.3728 8 9.8304 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 External Input Clock (MHz) 1.0000 1.2288 1.5000 1.8432 2.0000 2.4576 2.5000 2.7648 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.6080 4.9152 5.0000 Maximum Bit Rate (Bits/s) 62500 76800 93750 115200 125000 153600 156250 172800 187500 192000 218750 230400 250000 268800 281250 288000 307200 312500
Table 12.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)
(MHz) 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (Bits/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3
224
12.3
12.3.1
Operation
Overview
For serial communication, the SCI1 has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (SMR1), as shown in table 12.8. The SCI1 clock source is selected by the C/A bit in the serial mode register (SMR1) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 12.9. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. * An internal or external clock can be selected as the SCI1 clock source. When an internal clock is selected, the SCI1 operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Clock Synchronous Mode: * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCI1 clock source. When an internal clock is selected, the SCI1 operates using the on-chip baud rate generator clock, and outputs a synchronous clock signal to external devices. When an external clock is selected, the SCI1 operates on the input synchronous clock. The on-chip baud rate generator is not used.
225
Table 12.8 SMR1 Settings and SCI1 Communication Formats
SMR Settings Mode Asynchronous Bit 7 Bit 6 C/A CHR 0 0 Bit 5 PE 0 Bit 2 MP 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 0 * * 1 * * Clock synchronous 1 * * * 1 0 1 0 1 * 8-bit Not set 7-bit 8-bit Not set Set Set 7-bit Not set Set SCI1 Communication Format Data Length 8-bit Parity Bit Not set Multipro- Stop Bit cessor Bit Length Not set 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None
Note: Asterisks (*) in the table indicate don't-care bits.
Table 12.9 SMR1 and SCR1 Settings and SCI1 Clock Source Selection
SMR1 Mode Bit 7 C/A SCR1 Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Clock synchronous 1 0 0 1 1 0 1 Note: * Select the function in combination with the pin function controller (PFC). External Inputs the synchronous clock Internal Outputs the synchronous clock External SCI1 Transmit/Receive Clock Clock Source SCK Pin Function* Internal SCI1 does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate
Asynchronous 0
226
12.3.2
Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI1 are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI1 monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI1 synchronizes on the falling edge of the start bit. The SCI1 samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
Idling (marking state) 1 (MSB) D1 D2 D3 D4 D5 D6 D7 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 1 Stop bit
1 Serial data 0 Start bit
(LSB) D0
One unit of communication data (characters or frames)
Figure 12.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits)
227
Transmit/Receive Formats: Table 12.10 shows the 12 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR1). Table 12.10 Serial Communication Formats (Asynchronous Mode)
SMR1 Bits Bit 6: Bit 5: Bit 2: Bit 3: CHR PE MP STOP 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 11 12
START START START START START START START START START START START START
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data MPB MPB STOP
STOP STOP STOP P P STOP STOP STOP
STOP STOP P P STOP STOP STOP MPB MPB STOP STOP STOP STOP STOP STOP
--: Don't care bits. Note: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI1 transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR1) and bits CKE1 and CKE0 in the serial control register (SCR1) (table 12.9).
228
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI1 operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 12.3 so that the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 12.3 Output Clock and Communication Data Phase Relationship (Asynchronous Mode) SCI1 Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR1), then initialize the SCI1 as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR1). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR1), which retain their previous contents. Figure 12.4 is a sample flowchart for initializing the SCI1. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. Select the clock source in the serial control register (SCR1). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR1). 3. Write the value corresponding to the bit rate in the bit rate register (BRR1). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR1) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI1 to use the TxD or RxD pin. The initial states are the marking transmit state, and the idle receive state (waiting for a start bit).
229
Initialize Clear TE and RE bits to 0 in SCR1 Set CKE1 and CKE0 bits in SCR1 (TE and RE bits are 0) (1)
Select transmit/receive format in SMR1
(2)
Set value to BRR1 Wait
(3)
1-bit interval elapsed? Yes Set TE or RE to 1 in SCR1; Set RIE, TIE, TEIE, and MPIE as necessary
No
(4)
End
Figure 12.4 Sample Flowchart for SCI1 Initialization Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI1 initialization: Set the TxD pin using the PFC. 2. SCI1 status check and transmit data write: Read the serial status register (SSR1), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR1) and clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR1, then clear TDRE to 0. 4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0, then clear the TE to 0 in SCR1 and use the PFC to establish the TxD pin as an output port.
230
Initialize Start transmitting
(1)
Read TDRE bit in SSR1
(2) No
TDRE = 1? Yes Write transmission data to TDR1 and clear TDRE bit in SSR1 to 0 (3) All data transmitted? Yes Read TEND bit in SSR1
No
TEND = 1? Yes Output break signal? (4) Yes Set DR = 0 Clear TE bit in SCR1 to 0; select theTxD pin as an output port with the PFC
No
No
End transmission
Figure 12.5 Sample Flowchart for Transmitting Serial Data
231
In transmitting serial data, the SCI1 operates as follows: 1. The SCI1 monitors the TDRE bit in the SSR1. When TDRE is cleared to 0, the SCI1 recognizes that the transmit data register (TDR1) contains new data, and loads this data from the TDR1 into the transmit shift register (TSR1). 2. After loading the data from the TDR1 into the TSR1, the SCI1 sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR1, the SCI1 requests a transmit-data-empty interrupt (TxI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1 bits (stop bits) are output. e. Marking: output of 1 bits continues until the start bit of the next transmit data. 3. The SCI1 checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI1 loads new data from the TDR1 into the TSR1, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI1 sets the TEND bit to 1 in the SSR1, outputs the stop bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR1 is set to 1, a transmit-end interrupt (TEI) is requested. Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
232
1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0
Data D1
Parity Stop bit bit D7 0/1 1
1 Idle (marking state)
TDRE
TEND
TxI TxI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 1 frame
TxI interrupt request
TEI interrupt request
Figure 12.6 SCI1 Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Receiving Serial Data: Figures 12.7 show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). 1. SCI1 initialization: Set the RxD pin using the PFC. 2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of the SSR1 to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI1 status check and receive-data read: Read the serial status register (SSR1), check that RDRF is set to 1, then read receive data from the receive data register (RDR1) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read the RDR1 and RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received.
233
Initialization
(1)
Start reception
Read ORER, PER, and FER bits in SSR1
PER, FER, ORER = 1? No Read the RDRF bit in SSR1
Yes (2) Error handling (3)
No
RDRF = 1? Yes
Read reception data of RDR1 and clear RDRF bit in SSR1 to 0
(4)
No
All data received? Yes Clear the RE bit of SCR1 to 0
End reception
Figure 12.7 Sample Flowchart for Receiving Serial Data
234
Start of error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR1 to 0 Yes
No
PER = 1? Yes Parity error handling
Clear ORER, PER, and FER to 0 in SSR1 End
Figure 12.7 Sample Flowchart for Receiving Serial Data (cont)
235
In receiving, the SCI1 operates as follows: 1. The SCI1 monitors the communication line. When it detects a start bit (0), the SCI1 synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR1 in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI1 makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SMR1. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR1 into the RDR1. If the data passes these checks, the SCI1 sets RDRF to 1 and stores the received data in the RDR1. If one of the checks fails (receive error), the SCI1 operates as indicated in table 12.11. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR1, the SCI1 requests a receive-data-full interrupt (RxI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI1 requests a receive-error interrupt (ERI). Figure 12.8 shows an example of SCI1 receive operation in the asynchronous mode. Table 12.11 Receive Error Conditions and SCI1 Operation
Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SSR1 Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR1 Data Transfer Receive data not loaded from RSR1 into RDR1 Receive data loaded from RSR1 into RDR1 Receive data loaded from RSR1 into RDR1
236
1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0
Data D1
Parity Stop bit bit D7 0/1 0
1 Idle (marking state)
TDRF RxI interrupt request
FER
1 frame
RxI interrupt handler reads data in RDR and clears RDRF to 0.
Framing error generates ERI interrupt request.
Figure 12.8 SCI1 Receive Operation (8-Bit Data with Parity and One Stop Bit) 12.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 12.9 shows the example of communication among processors using the multiprocessor format.
237
Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 12.8. Clock: See the description in the asynchronous mode section.
Transmitting processor Serial communication line
Receiving processor A (ID = 01)
Receiving processor B (ID = 02)
Receiving processor C (ID = 03)
Receiving processor D (ID = 04)
Serial data
H'01 (MPB = 1) ID-transmit cycle: receiving processor address
H'AA (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID
MPB: Multiprocessor bit
Figure 12.9 Communication Among Processors Using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Transmitting Multiprocessor Serial Data: Figure 12.10 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI1 initialization: Set the TxD pin using the PFC. 2. SCI1 status check and transmit data write: Read the serial status register (SSR1), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR1). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR1. Finally, clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR1, then clear TDRE to 0. 4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then clear TE to 0 in SCR1 and set the TxD pin function as output port with the PFC.
238
Initialization Start transmission Read TDRE bit in SSR1
(1)
(2) No
TDRE = 1? Yes Write transmit data in TDR1 and set MPBT in SSR1 Clear TDRE bit to 0
All data transmitted? Yes Read TEND bit in SSR1
No
(3)
TEND = 1? Yes Output break signal? Yes Set DR = 0 Clear TE bit in SCR1 to 0; select theTxD pin function as an output port with the PFC
No
No (4)
End transmission
Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
239
In transmitting serial data, the SCI1 operates as follows: 1. The SCI1 monitors the TDRE bit in the SSR1. When TDRE is cleared to 0 the SCI1 recognizes that the transmit data register (TDR1) contains new data, and loads this data from the TDR1 into the transmit shift register (TSR1). 2. After loading the data from the TDR1 into the TSR1, the SCI1 sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR1 is set to 1, the SCI1 requests a transmit-data-empty interrupt (TxI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1 bits (stop bits) are output. e. Marking: output of 1 bits continues until the start bit of the next transmit data. 3. The SCI1 checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI1 loads data from the TDR1 into the TSR1, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI1 sets the TEND bit in the SSR1 to 1, outputs the stop bit, then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in the SCR1 is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 12.11 shows an example of SCI1 receive operation in the multiprocessor format.
Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 Multiprocessor bit Stop Data bit D1 D7 0/1 1
1 Serial data
Start bit 0
1 Idle (marking state)
TDRE
TEND
TxI interrupt TxI handler writes interrupt request data in TDR1 and clears TDRE to 0 1 frame
TxI interrupt request
TEI interrupt request
Figure 12.11 SCI1 Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit)
240
Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. SCI1 initialization: Set the RxD pin using the PFC. 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR1) to 1. 3. SCI1 status check and compare to ID reception: Read the serial status register (SSR1), check that RDRF is set to 1, then read data from the receive data register (RDR1) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR1 to identify the error. After executing the necessary error processing, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI1 status check and data receiving: Read SSR1, check that RDRF is set to 1, then read data from the receive data register (RDR1).
241
Initialization Start reception Set MPIE bit in SCR1 to 1 Read ORER and FER bits of SSR1 FER = 1? or ORER =1? No Read RDRF bit in SSR1 No
(1)
(2)
Yes
(3)
RDRF = 1? Yes Read receive data from RDR1
No
Is ID the station's ID Yes Read ORER and FER bits in SSR1 FER = 1? or ORER =1? No Read RDRF bit of SSR1 RDRF = 1? Yes Read receive data from RDR1 (4) (5) No Yes
No
All data received? Yes Clear RE bit in SCR1 to 0 End reception
Error processing
Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data
242
Start error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR1 to 0 Yes
Clear ORER and FER bits in SSR1 to 0
End
Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
243
Figures 12.13 show examples of SCI1 receive operation using a multiprocessor format.
Start bit 0 Data (ID1) D0 D1 D7 Stop Start Data MPB bit bit (data 1) 1 1 0 D0 D1 D7 Stop MPB bit 0 1
1 Serial data
1
Idling (marking)
MPB
MPIE
RDRF
RDR1 value RxI interrupt request (multiprocessor interrupt), MPIE = 0 RxI interrupt handler reads data in RDR1 and clears RDRF to 0
ID1
Not station's ID, so MPIE is set to 1 again
No RxI interrupt, RDR1 maintains state
(a) ID Does Not Match Start bit 0 Data (ID2) D0 D1 D7 Stop Start Data MPB bit bit (data 2) 1 1 0 D0 D1 D7 Stop MPB bit 0 1
1 Serial data
1
Idling (marking)
MPB
MPIE
RDRF
RDR1 value
ID1
ID2
Data2
RxI interrupt request (multiprocessor interrupt), MPIE = 0
RxI interrupt handler reads data in RDR1 and clears RDRF to 0
Station's ID, so receiving MPIE continues, with data bit is again received by the RxI set to 1 interrupt processing routine
(b) ID Matches
Figure 12.13 SCI1 Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit)
244
12.3.4
Clock Synchronous Operation
In the clock synchronous mode, the SCI1 transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI1 transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 12.14 shows the general format in clock synchronous serial communication.
Transfer direction One unit (character or frame) of communication data Synchronization clock * *
LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
MSB Bit 7
Note: * High except in continuous transmitting or receiving.
Figure 12.14 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In the clock synchronous mode, the SCI1 transmits or receives data by synchronizing with the falling edge of the synchronization clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI1 transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR1) and bits CKE1 and CKE0 in the serial control register (SCR1). See table 12.9. When the SCI1 operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI1 is not transmitting or receiving, the clock signal remains in the high state.
245
Note: An overrun error occurs only during the receive operation, and the sync clock is output until the RE bit is cleared to 0. When you want to perform a receive operation in onecharacter units, select external clock for the clock source. SCI1 Initialization (Clock Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR1), then initialize the SCI1 as follows. When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR1). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR1), which retain their previous contents. Figure 12.15 is a sample flowchart for initializing the SCI1. 1. Select the clock source in the serial control register (SCR1). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR1). 3. Write the value corresponding to the bit rate in the bit rate register (BRR1) unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR1) to 1. Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings.
246
Start of initialization
Clear TE and RE bits to 0 in SCR1
Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (TE and RE are 0)
(1)
Select transmit/receive format in SMR1
(2)
Set value in BRR1 Wait 1-bit interval elapsed? Yes Set TE and RE to 1 in SCR1; Set RIE, TIE, TEIE, and MPIE bits
(3)
No
(4)
End
Figure 12.15 Sample Flowchart for SCI Initialization Transmitting Serial Data (Clock Synchronous Mode): Figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI1 initialization: Set the TxD pin function with the PFC. 2. SCI1 status check and transmit data write: Read SSR1, check that the TDRE flag is 1, then write transmit data in TDR1 and clear the TDRE flag to 0. 3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that data can be written, write data in TDR1, then clear the TDRE flag to 0. When the DMAC or DTC is activated by a transmit-data-empty interrupt request (TxI) to write data in TDR1, the TDRE flag is checked and cleared automatically.
247
Initialize
(1)
Start transmitting
Read TDRE flag in SSR1
(2)
No TDRE = 1? Yes Write transmit data in TDR1 and clear TDRE flag to 0 in SSR1
No All data transmitted? (3) Yes Read TEND flag in SSR1
TEND = 1? Yes Clear TE bit to 0 in SCR1
No
End
Figure 12.16 Sample Flowchart for Serial Transmitting
248
Figure 12.17 shows an example of SCI1 transmit operation.
Transmit direction Synchronization clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDRE
TEND TxI request TxI interrupt handler writes data in TDR1 and clears TDRE to 0 1 frame TxI request TEI request
Figure 12.17 Example of SCI1 Transmit Operation SCI1 serial transmission operates as follows. 1. The SCI1 monitors the TDRE bit in the SSR1. When TDRE is cleared to 0 the SCI1 recognizes that the transmit data register (TDR1) contains new data and loads this data from the TDR1 into the transmit shift register (TSR1). 2. After loading the data from the TDR1 into the TSR1, the SCI1 sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR1 is set to 1, the SCI1 requests a transmit-data-empty interrupt (TxI) at this time. If clock output mode is selected, the SCI1 outputs eight synchronous clock pulses. If an external clock source is selected, the SCI1 outputs data in synchronization with the input clock. Data are output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI1 checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI1 loads data from the TDR1 into the TSR1, then begins serial transmission of the next frame. If TDRE is 1, the SCI1 sets the TEND bit in the SSR1 to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR1 is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state.
249
Receiving Serial Data (Clock Synchronous Mode): Figure 12.18 shows a sample flowchart for receiving serial data. When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is listed below: 1. SCI1 initialization: Set the RxD pin using the PFC. 2. Receive error handling: If a receive error occurs, read the ORER bit in SSR1 to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI1 status check and receive data read: Read the serial status register (SSR1), check that RDRF is set to 1, then read receive data from the receive data register (RDR1) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR1, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RxI) to read RDR1, the RDRF bit is cleared automatically so this step is unnecessary.
250
Initialization
(1)
Start reception
Read the ORER bit of SSR1 Yes ORER = 1? No Read RDRF bit of SSR1 No (3) (2) Error processing
RDRF = 1? Yes Read receive data from RDR1 and clear RDRF bit of SSR1 to 0 (4)
No All data received? Yes Clear RE bit of SCR1 to 0
End reception
Figure 12.18 Sample Flowchart for Serial Receiving
251
Error handling
Overrun error processing
Clear ORER bit of SSR1 to 0 End
Figure 12.18 Sample Flowchart for Serial Receiving (cont) Figure 12.19 shows an example of the SCI1 receive operation.
Transfer direction
Synchronization clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RxI request
Read data with RxI interrupt processing routine and clear RDRF bit to 0 1 frame
RxI request ERI interrupt request generated by overrun error
Figure 12.19 Example of SCI1 Receive Operation In receiving, the SCI1 operates as follows: 1. The SCI1 synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into the RSR1 in order from the LSB to the MSB. After receiving the data, the SCI1 checks that RDRF is 0 so that receive data can be loaded from the RSR1 into the RDR1. If this check passes, the SCI1 sets RDRF to 1 and stores the received data in the RDR1. If the check does not pass (receive error), the SCI1 operates as indicated in table 12.11 and no further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is
252
not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR1, the SCI1 requests a receive-data-full interrupt (RxI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR1 is also set to 1, the SCI1 requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI1 initialization: Set the TxD and RxD pins using the PFC. 2. SCI1 status check and transmit data write: Read the serial status register (SSR1), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR1) and clear TDRE to 0. The TxI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: If a receive error occurs, read the ORER bit in SSR1 to identify the error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI1 status check and receive data read: Read the serial status register (SSR1), check that RDRF is set to 1, then read receive data from the receive data register (RDR1) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR1, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Before the MSB (bit 7) of the current frame is received, read the TDRE bit and check that it is safe to write (if it reads 1); if so, write data in TDR1, then clear TDRE to 0. Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, simultaneously clear the TE bit and RE bit to 0, then simultaneously set the TE bit and RE bit to 1.
253
Initialization Start transmitting/receive
(1)
Read TDRE bit in SSR1 No
(2)
TDRE = 1? Yes Write transmission data in TDR1 and clear TDRE bit of SSR1 to 0
Read ORER bit of SSR1 Yes (3) Error handling (4)
ORER = 1? No Read RDRF bit of SSR1 No
RDRF = 1? Yes Read receive data of RDR1, and clear RDRF bit of SSR1 to 0 All data transmitted/and received Yes Clear TE and RE bits of SCR1 to 0 End transmission/reception (5)
No
Figure 12.20 Sample Flowchart for Serial Transmission
254
12.4
Interrupt
The SCI1 has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RxI), and transmit-data-empty (TxI). Table 12.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR1). Each interrupt request is sent separately to the interrupt controller. TxI is requested when the TDRE bit in the serial status register (SSR1) is set to 1. RxI is requested when the RDRF bit in the SSR1 is set to 1. ERI is requested when the ORER, FER, or PER bit in the SSR1 is set to 1. TEI is requested when the TEND bit in the SSR1 is set to 1. Where the TxI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation has ended. Table 12.12 SCI1 Interrupt Sources
Interrupt Source ERI RxI TxI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Low Priority High
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12.5
Notes on Use
The following points should be noted when using the SCI1. TDR1 Write and TDRE Flags: The TDRE bit in the serial status register (SSR1) is a status flag indicating loading of transmit data from TDR1 into TSR1. The SCI1 sets TDRE to 1 when it transfers data from TDR1 to TSR1. Data can be written to TDR1 regardless of the TDRE bit status. If new data is written in TDR1 when TDRE is 0, however, the old data stored in TDR1 will be lost because the data has not yet been transferred to the TSR1. Before writing transmit data to the TDR1, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 12.13 indicates the state of the SSR1 status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR1 contents cannot be transferred to the RDR1, so receive data is lost. Table 12.13 SSR1 Status Flags and Transfer of Receive Data
SSR1 Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR1 RDR1 X O O X X O X
Note: O = Receive data is transferred from RSR1 to RDR1. X = Receive data is not transferred from RSR1 to RDR1.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI1 receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port
256
using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the present transmission status. Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: The SCI1 operates on a base clock of 16 times the bit rate frequency in the asynchronous mode. In receiving, the SCI1 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 12.21).
16 clocks 8 clocks 0 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 78 15 0 78 15 0 5
Figure 12.21 Receive Data Sampling Timing in the Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as:
M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100%
M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute deviation of clock frequency
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
D = 0.5, F = 0 M = (0.5 - 1/(2 x 16)) x 100% = 46.875% 257
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%. Cautions for Clock Synchronous External Clock Mode * Set TE = RE = 1 only when the external clock SCK is 1. * Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed from 0 to 1. * When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the RxD D7 bit SCK input, but it cannot be copied to RDR. Caution for Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but it cannot be copied to RDR. Caution for SCI Register Initialization in Standby Mode: The SCR1, SMR1, and BRR1 registers incorporated into the serial communication interface (SCI) of the SH7018F user chip are not initialized in standby mode. Consequently, if a transition is made to standby mode while the TIE bit in SCR1 is set to 1, the TDRE bit in the serial status register (SSR1) will be set to 1, and after recovery from standby mode a transmit-data-empty interrupt (TXI) will be generated. When switching to standby mode, therefore, coding that initializes the SCR1, SMR1, and BRR1 registers must be inserted immediately before the relevant SLEEP instruction.
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Section 13 A/D Converter (A/D)
13.1 Overview
The A/D converter has 10-bit resolution, and can select from a maximum of eight channels of analog inputs. 13.1.1 Features
The A/D converter has the following features: * 10-bit resolution * Eight input channels * High-speed conversion Minimum conversion time: 6.7 s per channel (for 20-MHz operation) * Two operating modes: single mode or scan mode Single mode: A/D conversion on one channel Scan mode: Continuous A/D conversion on one to four channels * Four 16-bit data registers Conversion results transferred to and stored in data registers corresponding to each channel. * Sample and hold function * A/D conversion end interrupt generation An A/D conversion end interrupt (ADI) request can be generated on completion of A/D conversion. * A/D conversion can be started by MTU trigger input.
259
13.1.2
Block Diagram
Figure 13.1 is the block diagram of the A/D converter.
Module data bus
ADDRA
ADDRC
ADDRB
ADDRD
ADCSR
AVcc AVss 10-bit D/A
Successive approximations register
AN0
+
Analog multiplexer
AN1 AN2 AN3 AN4 AN5 AN6 AN7
- Comparator Control circuit Sample and hold circuit
ADCR
Bus interface
Internal data bus
/8
/16
ADI interrupt signal A/D converter ADCR: ADDCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D MTU trigger
Figure 13.1 A/D Converter Block Diagram
260
13.1.3
Pin Configuration
Table 13.1 shows the input pins used by the A/D converter. The seven analog input pins are divided into two groups: group 0, comprising analog input pins 0 to 3 (AN0 to AN3), and group 1, comprising analog input pins 4 to 7 (AN4 to AN7). The AVCC and AVSS pins are for the A/D converter internal analog section power supply. Table 13.1 Pin Configuration
Pin Analog supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O I I I I I I I I I I Analog input group 1 Function Analog section power supply Analog section ground and A/D conversion reference voltage Analog input group 0
261
13.1.4
Register Configuration
Table 13.2 shows the configuration of the A/D converter registers. Table 13.2 Register Configuration
Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL Abbreviation R/W ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL R R R R R R R R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FFFF8420 H'FFFF8421 H'FFFF8422 H'FFFF8423 H'FFFF8424 H'FFFF8425 H'FFFF8426 H'FFFF8427 H'FFFF8428 H'FFFF8429 Access Size 8,16 16 8,16 16 8,16 16 8,16 16 8,16 8,16
A/D control/status register ADCSR A/D control register ADCR
R/(W)* H'00 R/W H'7F
Note: * Only 0 can be written to bit 7 to clear the flag.
13.2
13.2.1
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
The A/D data registers (ADDR) are 16-bit read-only registers for storing A/D conversion results. There are four of these registers, ADDRA through ADDRD. The A/D-converted data is 10-bit data which is transferred to the ADDR for the selected channel for storage. The upper 8 bits of the converted data correspond to the upper byte of the ADDR, and the lower 2 bits correspond to the lower byte. Bits 5 to 0 of the lower byte of the ADDR are reserved. These bits are always read as 0. The write value should always be 0. Table 13.3 shows the correspondence between the analog input channels and the ADDR registers. The ADDR registers can be read by the CPU at all times. The upper byte is read directly, but the lower byte data is transferred via a temporary register (TEMP). For details, see section 13.3, CPU Interface. The ADDR registers are initialized to H'0000 by a power-on reset.
262
Bit: ADDRn: Initial value: R/W: Bit: ADDRn: Initial value: R/W: (n = A to D)
15 AD9 0 R 7 AD1 0 R
14 AD8 0 R 6 AD0 0 R
13 AD7 0 R 5 -- 0 R
12 AD6 0 R 4 -- 0 R
11 AD5 0 R 3 -- 0 R
10 AD4 0 R 2 -- 0 R
9 AD3 0 R 1 -- 0 R
8 AD2 0 R 0 -- 0 R
Table 13.3 Correspondence between Analog Input Channels and ADDRA-ADDRD
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD
13.2.2
A/D Control/Status Register (ADCSR)
The ADCSR is an 8-bit read/write register used for A/D conversion operation control and to indicate status. The ADCSR is initialized to H'00 by power-on reset.
Bit: 7 ADF Initial value: R/W: 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Note: * The only value that can be written is a 0 to clear the flag.
263
* Bit 7--A/D End Flag (ADF): This status flag indicates that A/D conversion has ended.
Bit 7: ADF 0 Description Clear conditions (Initial value)
With ADF = 1, by reading the ADF flag then writing 0 in ADF 1 Set conditions * * Single mode: When A/D conversion ends after conversion for all designated channels Scan mode: After one round of A/D conversion for all specified channels
* Bit 6--A/D Interrupt Enable (ADIE): Enables or disables interrupt requests (ADI) after A/D conversion ends.
Bit 6: ADIE 0 1 Description Disables interrupt requests (ADI) after A/D conversion ends (Initial value) Enables interrupt requests (ADI) after A/D conversion ends
* Bit 5--A/D Start (ADST): Selects start or stop for A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by MTU trigger input.
Bit 5: ADST 0 1 Description A/D conversion halted (Initial value)
Single mode: Start A/D conversion. Automatically cleared to 0 after conversion for the designated channel ends. Scan mode: Start A/D conversion. Continuous conversion until 0 cleared by software, and by power-on reset.
* Bit 4--Scan Mode (SCAN): Selects single mode or scan mode for A/D conversion. For details of the operation in single mode and scan mode, see section 13.4, Operation. Change the mode only when ADST = 0.
Bit 4: SCAN 0 1 Description Single mode Scan mode (Initial value)
264
* Bit 3--Clock Select (CKS): Sets the A/D conversion time. Change the conversion time only when ADST = 0.
Bit 3: CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value)
* Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits, along with the SCAN bit, select the analog input channel. Change the channel selection only when ADST = 0.
Description Bit 2: CH2 0 0 0 0 1 1 1 1 Bit 1: CH1 0 0 1 1 0 0 1 1 Bit 0: CH0 0 1 0 1 0 1 0 1 Single Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 (Initial value) Scan Mode AN0 (Initial value)
AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7
13.2.3
A/D Control Register (ADCR)
The A/D control register (ADCR) is an 8-bit read/write register that enables or disables starting of A/D conversion by MTU trigger input. The ADCR is initialized to H'7F by a power-on reset.
Bit: 7 TRGE Initial value: R/W: 0 R/W 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R
265
* Bit 7--Trigger Enable (TRGE): Enables or disables starting of A/D conversion by MTU trigger input.
Bit 7: TRGE 0 1 Description Disables A/D conversion start by MTU trigger input A/D conversion is started by MTU trigger (Initial value)
* Bits 6 to 0--Reserved: These bits are always read as 1. The write value should always be 1.
13.3
CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, while the upper byte is accessed directly by the CPU, the lower byte is accessed via an 8-bit temporary register (TEMP). Data is read from an ADDR register as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an ADDR register, always read the upper byte before the lower byte. This operation can be performed by reading ADDR from the upper byte address using a word transfer instruction (such as MOV.W). It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 13.2 shows the data flow for access to an ADDR register.
266
Upper-byte read Module data bus
CPU (H'AA)
Bus interface
TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read Module data bus
CPU (H'40)
Bus interface
TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D)
Figure 13.2 ADDR Access Operation (Reading H'AA40)
267
13.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode.. The operation in these two modes is described below. 13.4.1 Single Mode (SCAN = 0)
Single mode should be selected for A/D conversion on only one channel. A/D conversion starts when the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or MTU trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When conversion ends, the ADF bit in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an ADI interrupt is requested. To clear the ADF bit, first read ADF when set to 1, then write 0 in ADF. To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0 before changing the mode or analog input channel. After the change is made, A/D conversion is restarted by setting the ADST bit to 1 (the mode or channel change and setting of the ADST bit can be carried out simultaneously). An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion is performed in single mode is described below. Figure 13.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt request is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time ADF is set to 1, ADST is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt service routine is started. 5. The routine reads ADF set to 1, then writes 0 in ADF. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt service routine ends. After this, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated.
268
Set*
ADIE Set* A/D conversion starts Clear* Clear* Set*
ADST
ADF Conversion standby
Channel 0 (AN0) Conversion standby A/D conversion 1 Conversion standby
Channel 1 (AN1) Conversion standby
A/D conversion 2
Conversion standby
Channel 2 (AN2) Conversion standby
Channel 3 (AN3)
ADDRA Conversion result read A/D conversion result 1 Conversion result read A/D conversion result 2
ADDRB
ADDRC
ADDRD
Figure 13.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Note: * Vertical arrows ( ) indicate instructions executed by software.
269
13.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or MTU trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH1 = 1). When more than one channel has been selected, A/D conversion starts on the second channel (AN1 or AN5) as soon as conversion ends on the first channel. A/D conversion is performed repeatedly on all the selected channels until the ADST bit is cleared to 0. The conversion results are transferred to and stored in the ADDR register for each channel. To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0 before changing the mode or analog input channels. After the change is made, the first channel is selected and A/D conversion is restarted by setting the ADST bit to 1 (the mode or channel change and setting of the ADST bit can be carried out simultaneously). An example of the A/D conversion operation in scan mode when three channels (AN0 to AN2) in group 0 are selected is described below. Figure 13.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), group 0 is selected as the scan group (CH2 = 0), analog input channels AN0-AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. A/D conversion starts on the first channel (AN0), and when completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion is completed for all the selected channels (AN0 to AN2), ADF is set to 1, the first channel (AN0) is selected again, and conversion is performed on that channel. If the ADIE bit is also 1, an ADI interrupt is requested when conversion is completed. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
270
Continuous A/D conversion
1 Set*
Clear*
1
ADST Clear* A/D conversion time A/D conversion 1 Conversion standby A/D conversion 4 Conversion standby
1
ADF
hannel 0 (AN0) Conversion standby A/D conversion 2 Conversion standby
Conversion standby
hannel 1 (AN1) Conversion standby A/D conversion 3
2 A/D conversion 5 *
Conversion standby
hannel 2 (AN2) Conversion standby Transfer A/D conversion result 1
hannel 3 (AN3)
ADDRA
A/D conversion result 4
ADDRB
A/D conversion result 2
ADDRC
A/D conversion result 3
ADDRD
Figure 13.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored.
271
13.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample and hold circuit. The A/D converter samples the analog input at time tD after the ADST bit is set to 1 in the A/D control/status register (ADCSR), then starts conversion. Figure 13.5 shows the A/D conversion timing, and table 13.4 shows A/D conversion times. As shown in figure 13.5, A/D conversion time tCONV consists of A/D conversion start delay time tD and analog input sampling time tSPL. The length of tD is not fixed, but is determined by the timing of the write to ADSCR. The total conversion time therefore varies within the ranges shown in table 13.4. In scan mode, the tCONV values given in table 13.4 apply to the first conversion. In the second and subsequent conversions, tCONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
272
(1) CK
Address
(2)
Write signal
Input sampling timing
ADF tD tSPL tCONV (1): (2): tD: tSPL: tCONV: ADCSR write cycle ADCSR address A/D conversion start delay time Input sampling time A/D conversion time
Figure 13.5 A/D Conversion Timing Table 13.4 A/D Conversion Times (Single Mode)
CKS = 0 Symbol A/D conversion start delay time Input sampling time A/D conversion time Note: Unit: states (tcyc ) tD t SPL t CCNV Min 10 -- 259 Typ -- 64 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 32 -- Max 9 -- 134
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13.4.4
MTU Trigger Input Timing
A/D conversion can also be started by MTU trigger input. When the TRGE bit is set to 1 in the A/D control register (ADCR), input from the MTU functions as trigger input. When an MTU trigger is detected, the ADST bit is set to 1 in the A/D control/status register (ADST), and the A/D converter is started. Other operations, for both single mode and scan mode, are the same as when the ADST bit is set to 1 by software, . Figure 13.6 shows the timing for MTU trigger input.
CK
MTU trigger signal
ADST A/D conversion
Figure 13.6 External Trigger Input Timing
13.5
A/D Conversion Precision Definitions
The A/D converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. In this operation, the absolute precision of the A/D conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. 1. 2. 3. 4. Offset error Full-scale error Quantization error Nonlinearity error
274
The above four kinds of error are described below with reference to figure 13.7. For the sake of clarity, this figure shows 3-bit A/D conversion rather than 10-bit A/D conversion. Offset error (see figure 13.7 (1)) is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). Full-scale error (see figure 13.7 (2)) is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 111111111 (111 in the figure). Quantization error is the deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.7 (3)). Nonlinearity error is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic from zero voltage to full-scale voltage (see figure 13.7 (4)). This does not include offset error, full-scale error, and quantization error.
(2) Full-scale error
Digital output
Digital output
111 110 101 100 011 010 001 000 0
Ideal A/D conversion characteristic
Ideal A/D conversion characteristic
(4) Nonlinearity error (3) Quantization error Actual A/D conversion characteristic
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS FS
Analog input voltage FS: Full-scale voltage
(1) Offset error
Analog input voltage
Figure 13.7
A/D Conversion Precision Definitions
275
13.6
Notes on Use
The following points should be noted when using the A/D converter. 13.6.1 Analog Voltage Settings
Analog Input Voltage Range: The voltage applied to analog input pins during A/D conversion should be in the range AVSS ANn AVCC (n = 0 to 7). AVCC and AV SS input voltages: For the AV CC and AVSS input voltages, set AVCC = 3.3 V 10%, and AVSS = VSS . When the A/D converter is not used, set AVCC = VCC and AVSS = VSS . 13.6.2 Handling of Analog Input Pins
To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to AN7), connect a protection circuit such as that shown in figure 13.8. This circuit also includes a CR filter function that suppresses error due to noise. The circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. Figure 13.9 shows an equivalent circuit for the analog input pins, and table 13.5 summarizes the analog input pin specifications.
AVcc 100 AN0 to AN7 * 0.1 F AVss SH7018
Note:
10 F
0.01 F
Figure 13.8 Example of Analog Input Pin Protection Circuit
276
1.0 k AN0 to AN7
20 pF
1 M
Analog multiplexer Note: Values are reference values.
A/D converter
Figure 13.9 Analog Input Pin Equivalent Circuit Table 13.5 Analog Input Pin Specifications
Item Analog input capacitance Permitted signal source impedance Min -- -- Max 20 3 Unit pF k
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278
Section 14 Pin Function Controller (PFC)
14.1 Overview
The pin function controller (PFC) consists of registers for selecting multiplex pin functions and their input/output direction. Table 14.1 shows the SH7018's multiplex pins. The functions of the multiplex pins are determined by the operating mode. Table 14.2 and table 14.3 show the pin functions in each operating mode and the initial values. Table 14.1 Multiplex Pins
Port A A A A A A A A A A A A A A A B B B B B B B B Function 1 (Related Module) PA15 I/O (port) PA14 I/O (port) PA12 I/O (port) PA11 I/O (port) PA10 I/O (port) PA9 I/O (port) PA8 I/O (port) PA7 I/O (port) PA6 I/O (port) PA5 I/O (port) PA4 I/O (port) PA3 I/O (port) PA2 I/O (port) PA1 I/O (port) PA0 I/O (port) PB9 I/O (port) PB8 I/O (port) PB7 I/O (port) PB6 I/O (port) PB5 I/O (port) PB4 I/O (port) PB3 I/O (port) PB2 I/O (port) IRQ1 input (INTC) A18 output (BSC) IRQ7 input (INTC) IRQ6 input (INTC) A21 output (BSC) A20 output (BSC) A19 output (BSC) WAIT input (BSC) SCK I/O (SCI) TXD output (SCI) RXD input (SCI) IRQ0 input (INTC) Function 2 (Related Module) CK output (CPG) RD output (BSC) WRL output (BSC) CS1 output (BSC) CS0 output (BSC) IRQ3 (INTC) IRQ2 (INTC) CS3 output (BSC) CS2 output (BSC) Function 3 (Related Module) Function 4 (Related Module) Pin No. 75 33 34 35 36 42 44 37 38 47 48 49 50 40 41 31 46 29 28 27 26 24 23
279
Table 14.1 Multiplex Pins (cont)
Port B B C C C C C C C C C C C C C C C C D D D D D D D D E E E E E Function 1 (Related Module) PB1 I/O (port) PB0 I/O (port) PC15 I/O (port) PC14 I/O (port) PC13 I/O (port) PC12 I/O (port) PC11 I/O (port) PC10 I/O (port) PC9 I/O (port) PC8 I/O (port) PC7 I/O (port) PC6 I/O (port) PC5 I/O (port) PC4 I/O (port) PC3 I/O (port) PC2 I/O (port) PC1 I/O (port) PC0 I/O (port) PD7 I/O (port) PD6 I/O (port) PD5 I/O (port) PD4 I/O (port) PD3 I/O (port) PD2 I/O (port) PD1 I/O (port) PD0 I/O (port) PE14 I/O (port) PE13 I/O (port) PE12 I/O (port) PE11 I/O (port) PE10 I/O (port) Function 2 (Related Module) A17 output (BSC) A16 output (BSC) A15 output (BSC) A14 output (BSC) A13 output (BSC) A12 output (BSC) A11 output (BSC) A10 output (BSC) A9 output (BSC) A8 output (BSC) A7 output (BSC) A6 output (BSC) A5 output (BSC) A4 output (BSC) A3 output (BSC) A2 output (BSC) A1 output (BSC) A0 output (BSC) D7 I/O (BSC) D6 I/O (BSC) D5 I/O (BSC) D4 I/O (BSC) D3 I/O (BSC) D2 I/O (BSC) D1 I/O (BSC) D0 I/O (BSC) Function 3 (Related Module) Function 4 (Related Module) Pin No. 21 20 19 18 17 16 14 13 12 11 10 9 7 6 5 4 3 2 53 54 56 58 59 60 61 62 88 87 86 85 84
280
Table 14.1 Multiplex Pins (cont)
Port E E E E E E E E F F F F F F F F Function 1 (Related Module) PE9 I/O (port) PE8 I/O (port) PE7 I/O (port) PE6 I/O (port) PE5 I/O (port) PE4 I/O (port) PE2 I/O (port) PE0 I/O (port) PF7 input (port) PF6 input (port) PF5 input (port) PF4 input (port) PF3 input (port) PF2 input (port) PF1 input (port) PF0 input (port) TIOC2B I/O (MTU) TIOC2A I/O (MTU) TIOC1B I/O (MTU) TIOC1A I/O (MTU) TIOC0C I/O (MTU) TIOC0A I/O (MTU) AN7 input (A/D) AN6 input (A/D) AN5 input (A/D) AN4 input (A/D) AN3 input (A/D) AN2 input (A/D) AN1 input (A/D) AN0 input (A/D) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) Pin No. 83 82 81 80 78 77 64 63 98 97 95 94 93 92 91 90
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14.2
Register Configuration
The PFC registers are listed in table 14.3. Table 14.3 PFC Registers
Name Port A IO register L Port A control register L1 Port A control register L2 Port B IO register Port B control register 1 Port B control register 2 Port C IO register Port C control register Port D IO register L Port D control register L Port E IO register Port E control register 2 Abbreviation PAIORL PACRL1 PACRL2 PBIOR PBCR1 PBCR2 PCIOR PCCR PDIORL PDCRL PEIOR PECR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'4000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFF8386 H'FFFF8387 H'FFFF838C H'FFFF838D H'FFFF838E H'FFFF838F H'FFFF8394 H'FFFF8395 H'FFFF8398 H'FFFF8399 H'FFFF839A H'FFFF839B H'FFFF8396 H'FFFF8397 H'FFFF839C H'FFFF839D H'FFFF83A6 H'FFFF83A7 H'FFFF83AC H'FFFF83AD H'FFFF83B4 H'FFFF83B5 H'FFFF83BA H'FFFF83BB Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
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14.3
14.3.1
Register Descriptions
Port A IO Register L (PAIORL)
Port A IO register L (PAIORL) is a 16-bit readable/writable register that selects the input/output direction of the pins in port A. The bits of this register correspond to the various pins. PAIORL is enabled when the port A pins function as general input/output (PA15 to PA0) or serial clock (SCK) pins, and disabled otherwise. When the port A pins function as PA15 to PA0 or SCK, a pin becomes an output when the corresponding bit in PAIORL is set to 1, and an input when the bit is cleared to 0. PAIORL is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15 14 13 -- 0 R 5 12 11 10 9 8
PA15IOR PA14IOR Initial value: R/W: Bit: 0 R/W 7 PA7IOR Initial value: R/W: 0 R/W 0 R/W 6
PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR 0 R/W 4 0 R/W 3 0 R/W 2 PA2IOR 0 R/W 0 R/W 1 0 R/W 0
PA6IOR PA5IOR 0 R/W 0 R/W
PA4IOR PA3IOR 0 R/W 0 R/W
PA1IOR PA0IOR 0 R/W 0 R/W
14.3.2
Port A Control Registers L1 and L2 (PACRL1, PACRL2)
Port A control registers L1 and L2 (PACRL1, PACRL2) are 16-bit readable/writable registers that select the functions of the pins in port A. PACRL1 is initialized to H'4000 by an external power-on reset. PACRL2 is initialized to H'0000 by an external power-on reset. However, they are not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases they retain their previous data.
283
Port A Control Register L1 (PACRL1)
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PA15MD 1 R/W 6 PA11MD0 0 R/W 13 -- 0 R 5 -- 0 R 12 PA14MD 0 R/W 4 11 -- 0 R 3 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 PA8MD1 0 R/W 8 PA12MD 0 R/W 0 -- 0 R
PA10MD PA9MD1 0 R/W 0 R/W
Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. Bit 14--PA15 Mode (PA15MD): Selects the function of the PA15/CK pin.
Bit 14: PA15MD 0 1 Description General input/output (PA15) Clock output (CK) (Initial value)
Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. Bit 12--PA14 Mode (PA14MD): Selects the function of the PA14/RD pin.
Bit 12: PA14MD 0 1 Description General input/output (PA14) Read output (RD) (Initial value)
Bits 11 to 9--Reserved: These bits are always read as 0. The write value should always be 0. Bit 8--PA12 Mode (PA12MD): Selects the function of the PA12/WRL pin.
Bit 8: PA12MD 0 1 Description General input/output (PA12) Chip select output (WRL) (Initial value)
Bit 7--Reserved: These bits are always read as 0. The write value should always be 0.
284
Bit 6--PA11 Mode (PA11MD): Selects the function of the PA11/CS1 pin.
Bit 6: PA11MD 0 1 Description General input/output (PA11) Chip select output (CS1) (Initial value)
Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. Bit 4--PA10 Mode (PA10MD): Selects the function of the PA10/CS0 pin.
Bit 4: PA10MD 0 1 Description General input/output (PA10) Chip select output (CS0) (Initial value)
Bit 3--PA9 Mode 1 (PA9MD1): This bit selects the function of the PA9/IRQ3 pin.
Bit 3: PA9MD1 0 1 Description General input/output (PA9) Interrupt request input (IRQ3) (Initial value)
Bit 2--Reserved: This bit is always read as 0. The write value should always be 0. Bit 1--PA8 Mode 1 (PA8MD1): This bit selects the function of the PA8/IRQ2 pin.
Bit 1: PA8MD1 0 1 Description General input/output (PA8) Interrupt request input (IRQ2) (Initial value)
Bit 0--Reserved: This bit is always read as 0. The write value should always be 0.
285
Port A Control Register L2 (PACRL2)
Bit: 15 PA7MD1 Initial value: R/W: Bit: 0 R/W 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 13 PA6MD1 0 R/W 5 12 -- 0 R 4 11 -- 0 R 3 -- 0 R 10 PA5MD0 0 R/W 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 PA4MD 0 R/W 0 -- 0 R
PA3MD PA2MD1 PA2MD0 0 R/W 0 R/W 0 R/W
Bit 15--PA7 Mode 1 (PA7MD1): This bit selects the function of the PA7/CS3 pin.
Bit 15: PA7MD1 0 1 Description General input/output (PA7) Chip select output (CS3) (Initial value)
Bit 14--Reserved: This bit is always read as 0. The write value should always be 0. Bit 13--PA6 Mode 1 (PA6MD1): This bit selects the function of the PA6/CS2 pin.
Bit 13: PA6MD1 0 1 Description General input/output (PA6) Chip select output (CS2) (Initial value)
Bit 12--Reserved: This bit is always read as 0. The write value should always be 0. Bit 10--PA5 Mode 0 (PA5MD0): Selects the function of the PA5/SCK pin.
Bit 10: PA5MD0 0 1 Description General input/output (PA5) Serial clock input/output (SCK1) (Initial value)
Bits 11 and 9--Reserved: These bits are always read as 0. The write value should always be 0.
286
Bit 8--PA4 Mode (PA4MD): Selects the function of the PA4/TXD pin.
Bit 8: PA4MD 0 1 Description General input/output (PA4) Transmit data output (TXD) (Initial value)
Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Bit 6--PA3 Mode (PA3MD): Selects the function of the PA3/RXD pin.
Bit 6: PA3MD 0 1 Description General input/output (PA3) Receive data input (RXD) (Initial value)
Bits 5 and 4--PA2 Mode 1 and 0 (PA2MD1, PA2MD0): These bits select the function of the PA2/IRQ0 pin.
Bit 5: PA2MD1 0 Bit 4: PA2MD0 0 1 1 0 1 Description General input/output (PA2) Reserved Reserved Interrupt request input (IRQ0) (Initial value)
Bits 3 to 0--Reserved: These bits are always read as 0. The write value should always be 0.
287
14.3.3
Port B IO Register (PBIOR)
The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output direction of the pins in port B. The bits of this register correspond to the various pins. PBIOR is enabled when the port B pins function as general input/output (PB9 to PB0) pins, and disabled otherwise. When the port B pins function as PB9 to PB0, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PB7IOR Initial value: R/W: 0 R/W 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 PB2IOR 0 R/W 9 8
PB9IOR PB8IOR 0 R/W 1 0 R/W 0
PB6IOR PB5IOR 0 R/W 0 R/W
PB4IOR PB3IOR 0 R/W 0 R/W
PB1IOR PB0IOR 0 R/W 0 R/W
14.3.4
Port B Control Registers 1 and 2 (PVCR1, PBCR2)
Port B control registers 1 and 2 (PVCR1, PBCR2) are 16-bit readable/writable registers that select the functions of the pins in port B. PVCR1 and PBCR2 are each initialized to H'0000 by an external power-on reset. However, they are not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases they retain their previous data.
288
Port B Control Register 1 (PBCR1)
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0
PB9MD1 PB9MD0 PB8MD1 PB8MD0 0 R/W 0 R/W 0 R/W 0 R/W
Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Bits 3 and 2--PB9 Mode 1 and 0 (PB9MD1, PB9MD0): These bits select the function of the PB9/IRQ7/A21 pin.
Bit 3: PB9MD1 0 Bit 2: PB9MD0 0 1 1 0 1 Description General input/output (PB9) Interrupt request input (IRQ7) Address output (A21) Reserved (Initial value)
Bits 1 and 0--PB8 Mode 1 and 0 (PB8MD1, PB8MD0): These bits select the function of the PB8/IRQ6/A20/WAIT pin.
Bit 1: PB8MD1 0 Bit 0: PB8MD0 0 1 1 0 1 Description General input/output (PB8) Interrupt request input (IRQ6) Address output (A20) Wait state request input (WAIT) (Initial value)
289
Port B Control Register 2 (PBCR2)
Bit: 15 14 13 12 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 PB1MD 0 R/W 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 PB0MD 0 R/W
PB7MD1 PB7MD0 PB6MD1 PB6MD0 Initial value: R/W: Bit: 0 R/W 7 -- Initial value: R/W: 0 R 0 R/W 6 PB3MD0 0 R/W 0 R/W 5 -- 0 R 0 R/W 4 -- 0 R
Bits 15 and 14--PB7 Mode 1 and 0 (PB7MD1, PB7MD0): These bits select the function of the PB7/A19 pin.
Bit 15: PB7MD1 0 Bit 14: PB7MD0 0 1 1 0 1 Description General input/output (PB7) Reserved Address output (A19) Reserved (Initial value)
Bits 13 and 12--PB6 Mode 1 and 0 (PB6MD1, PB6MD0): These bits select the function of the PB6/A18 pin.
Bit 13: PB6MD1 0 Bit 12: PB6MD0 0 1 1 0 1 Description General input/output (PB6) Reserved Address output (A18) Reserved (Initial value)
Bits 11 to 7--Reserved: These bits are always read as 0. The write value should always be 0. Bit 6--PB3 Mode 0 (PB3MD0): Selects the function of the PB3/IRQ1 pin.
Bit 6: PB3MD0 0 1 Description General input/output (PB3) Interrupt request input (IRQ1) (Initial value)
Bits 5 to 3--Reserved: These bits are always read as 0. The write value should always be 0.
290
Bit 2--PB1 Mode (PB1MD): Selects the function of the PB1/A17 pin.
Bit 2: PB1MD 0 1 Description General input/output (PB1) Address output (A17) (Initial value)
Bit 1--Reserved: This bit is always read as 0 and should only be written with 0. Bit 0--PB0 Mode (PB0MD): Selects the function of the PB0/A16 pin.
Bit 0: PB0MD 0 1 Description General input/output (PB0) Address output (A16) (Initial value)
14.3.5
Port C IO Register (PCIOR)
The port C IO register (PCIOR) is a 16-bit readable/writable register that selects the input/output direction of the pins in port C. The bits of this register correspond to the various pins. PCIOR is enabled when the port C pins function as general input/output (PC15 to PC0) pins, and disabled otherwise. When the port C pins function as PC15 to PC0, a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15 14 13 12 11 10 9 8
PC15IOR PC14IOR PC13IOR PC12IOR PC11IOR PC10IOR PC9IOR PC8IOR Initial value: R/W: Bit: 0 R/W 7 PC7IOR Initial value: R/W: 0 R/W 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 PC2IOR 0 R/W 0 R/W 1 0 R/W 0
PC6IOR PC5IOR 0 R/W 0 R/W
PC4IOR PC3IOR 0 R/W 0 R/W
PC1IOR PC0IOR 0 R/W 0 R/W
291
14.3.6
Port C Control Register (PCCR)
The port C control register (PCCR) is a 16-bit readable/writable register that selects the functions of the pins in port C. PCCR is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases they retain their previous data.
Bit: 15 14 13 12 11 10 9 PC9MD 0 R/W 1 PC1MD 0 R/W 8 PC8MD 0 R/W 0 PC0MD 0 R/W
PC15MD PC14MD PC13MD PC12MD PC11MD PC10MD Initial value: R/W: Bit: 0 R/W 7 PC7MD Initial value: R/W: 0 R/W 0 R/W 6 PC6MD 0 R/W 0 R/W 5 PC5MD 0 R/W 0 R/W 4 PC4MD 0 R/W 0 R/W 3 PC3MD 0 R/W 0 R/W 2 PC2MD 0 R/W
Bit 15--PC15 Mode (PC15MD): Selects the function of the PC15/A15 pin.
Bit 15: PC15MD 0 1 Description General input/output (PC15) Address output (A15) (Initial value)
Bit 14--PC14 Mode (PC14MD): Selects the function of the PC14/A14 pin.
Bit 14: PC14MD 0 1 Description General input/output (PC14) Address output (A14) (Initial value)
Bit 13--PC13 Mode (PC13MD): Selects the function of the PC13/A13 pin.
Bit 13: PC13MD 0 1 Description General input/output (PC13) Address output (A13) (Initial value)
292
Bit 12--PC12 Mode (PC12MD): Selects the function of the PC12/A12 pin.
Bit 12: PC12MD 0 1 Description General input/output (PC12) Address output (A12) (Initial value)
Bit 11--PC11 Mode (PC11MD): Selects the function of the PC11/A11 pin.
Bit 11: PC11MD 0 1 Description General input/output (PC11) Address output (A11) (Initial value)
Bit 10--PC10 Mode (PC10MD): Selects the function of the PC10/A10 pin.
Bit 10: PC10MD 0 1 Description General input/output (PC10) Address output (A10) (Initial value)
Bit 9--PC9 Mode (PC9MD): Selects the function of the PC9/A9 pin.
Bit 9: PC9MD 0 1 Description General input/output (PC9) Address output (A9) (Initial value)
Bit 8--PC8 Mode (PC8MD): Selects the function of the PC8/A8 pin.
Bit 8: PC8MD 0 1 Description General input/output (PC8) Address output (A8) (Initial value)
Bit 7--PC7 Mode (PC7MD): Selects the function of the PC7/A7 pin.
Bit 7: PC7MD 0 1 Description General input/output (PC7) Address output (A7) (Initial value)
293
Bit 6--PC6 Mode (PC6MD): Selects the function of the PC6/A6 pin.
Bit 6: PC6MD 0 1 Description General input/output (PC6) Address output (A6) (Initial value)
Bit 5--PC5 Mode (PC5MD): Selects the function of the PC5/A5 pin.
Bit 5: PC5MD 0 1 Description General input/output (PC5) Address output (A5) (Initial value)
Bit 4--PC4 Mode (PC4MD): Selects the function of the PC4/A4 pin.
Bit 4: PC4MD 0 1 Description General input/output (PC4) Address output (A4) (Initial value)
Bit 3--PC3 Mode (PC3MD): Selects the function of the PC3/A3 pin.
Bit 3: PC3MD 0 1 Description General input/output (PC3) Address output (A3) (Initial value)
Bit 2--PC2 Mode (PC2MD): Selects the function of the PC2/A2 pin.
Bit 2: PC2MD 0 1 Description General input/output (PC2) Address output (A2) (Initial value)
Bit 1--PC1 Mode (PC1MD): Selects the function of the PC1/A1 pin.
Bit 1: PC1MD 0 1 Description General input/output (PC1) Address output (A1) (Initial value)
294
Bit 0--PC0 Mode (PC0MD): Selects the function of the PC0/A0 pin.
Bit 0: PC0MD 0 1 Description General input/output (PC0) Address output (A0) (Initial value)
14.3.7
Port D IO Register L (PDIORL)
Port D IO register L (PDIORL) is a 16-bit readable/writable register that selects the input/output direction of the pins in port D. The bits of this register correspond to the various pins. PDIORL is enabled when the port D pins function as general input/output (PD7 to PD0), and disabled otherwise. When the port D pins function as PD7 to PD0, a pin becomes an output when the corresponding bit in PDIORL is set to 1, and an input when the bit is cleared to 0. PDIORL is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PD7IOR Initial value: R/W: 0 R/W 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 PD2IOR 0 R/W 9 -- 0 R 1 8 -- 0 R 0
PD6IOR PD5IOR 0 R/W 0 R/W
PD4IOR PD3IOR 0 R/W 0 R/W
PD1IOR PD0IOR 0 R/W 0 R/W
295
14.3.8
Port D Control Register L (PDCRL)
Port D control register L (PDCRL) is a 16-bit readable/writable register that selects the functions of the pins in port D.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PD7MD Initial value: R/W: 0 R/W 14 -- 0 R 6 PD6MD 0 R/W 13 -- 0 R 5 PD5MD 0 R/W 12 -- 0 R 4 PD4MD 0 R/W 11 -- 0 R 3 PD3MD 0 R/W 10 -- 0 R 2 PD2MD 0 R/W 9 -- 0 R 1 PD1MD 0 R/W 8 -- 0 R 0 PD0MD 0 R/W
* On-Chip ROM Enabled Extended Mode Port D pins function as both data I/O pins and general I/O pins. PDCRL settings are enabled. PDCRL is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases they retain their previous data. Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Bit 7--PD7 Mode (PD7MD): Selects the function of the PD7/D7 pin.
Bit 7: PD7MD 0 1 Description General input/output (PD7) Data input/output (D7) (Initial value)
Bit 6--PD6 Mode (PD6MD): Selects the function of the PD6/D6 pin.
Bit 6: PD6MD 0 1 Description General input/output (PD6) Data input/output (D6) (Initial value)
Bit 5--PD5 Mode (PD5MD): Selects the function of the PD5/D5 pin.
Bit 5: PD5MD 0 1 296 Description General input/output (PD5) Data input/output (D5) (Initial value)
Bit 4--PD4 Mode (PD4MD): Selects the function of the PD4/D4 pin.
Bit 4: PD4MD 0 1 Description General input/output (PD4) Data input/output (D4) (Initial value)
Bit 3--PD3 Mode (PD3MD): Selects the function of the PD3/D3 pin.
Bit 3: PD3MD 0 1 Description General input/output (PD3) Data input/output (D3) (Initial value)
Bit 2--PD2 Mode (PD2MD): Selects the function of the PD2/D2 pin.
Bit 2: PD2MD 0 1 Description General input/output (PD2) Data input/output (D2) (Initial value)
Bit 1--PD1 Mode (PD1MD): Selects the function of the PD1/D1 pin.
Bit 1: PD1MD 0 1 Description General input/output (PD1) Data input/output (D1) (Initial value)
Bit 0--PD0 Mode (PD0MD): Selects the function of the PD0/D0 pin.
Bit 0: PD0MD 0 1 Description General input/output (PD0) Data input/output (D0) (Initial value)
297
14.3.9
Port E IO Register (PEIOR)
The port E IO register (PEIOR) is a 16-bit readable/writable register that selects the input/output direction of the pins in port E. The bits of this register correspond to the various pins. PEIOR is enabled when the port E pins function as general input/output (PE14 to PE4, PE2, and PE0) pins or TIOC pins for the MTU, and disabled otherwise. When the port E pins function as PE14 to PE4, PE2, and PE0 pins or TIOC pins for the MTU, a pin becomes an output when the corresponding bit in PEIOR is set to 1, and an input when the bit is cleared to 0. PEIOR is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PE7IOR Initial value: R/W: 0 R/W 14 13 12 11 10 9 8
PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR 0 R/W 6 0 R/W 5 0 R/W 4 PE4IOR 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 PE2IOR 0 R/W 0 R/W 1 -- 0 R 0 R/W 0 PE0IOR 0 R/W
PE6IOR PE5IOR 0 R/W 0 R/W
298
14.3.10
Port E Control Register 2 (PECR2)
Port E control register 2 (PECR2) is a 16-bit readable/writable register that selects the functions of the pins in port E. PECR2 is initialized to H'0000 by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PE7MD 0 R/W 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 PE6MD 0 R/W 4 PE2MD0 0 R/W 11 -- 0 R 3 -- 0 R 10 PE5MD 0 R/W 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 PE4MD 0 R/W 0 PE0MD0 0 R/W
Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. Bit 14--PE7 Mode (PE7MD): Selects the function of the PE7/TIOC2B pin.
Bit 14: PE7MD 0 1 Description General input/output (PE7) MTU input capture input/output compare output (TIOC2B) (Initial value)
Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. Bit 12--PE6 Mode (PE6MD): Selects the function of the PE6/TIOC2A pin.
Bit 12: PE6MD 0 1 Description General input/output (PE6) MTU input capture input/output compare output (TIOC2A) (Initial value)
Bit 11--Reserved: This bit is always read as 0. The write value should always be 0.
299
Bit 10--PE5 Mode (PE5MD): Selects the function of the PE5/TIOC1B pin.
Bit 10: PE5MD 0 1 Description General input/output (PE5) MTU input capture input/output compare output (TIOC1B) (Initial value)
Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. Bit 8--PE4 Mode (PE4MD): Selects the function of the PE4/TIOC1A pin.
Bit 8: PE4MD 0 1 Description General input/output (PE4) MTU input capture input/output compare output (TIOC1A) (Initial value)
Bits 7 to 5--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--PE2 Mode 0 (PE2MD0): Selects the function of the PE2/TIOC0C pin.
Bit 4: PE2MD0 0 1 Description General input/output (PE2) MTU input capture input/output compare output (TIOC0C) (Initial value)
Bits 3 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--PE0 Mode 0 (PE0MD0): Selects the function of the PE0/TIOC0A pin.
Bit 0: PE0MD0 0 1 Description General input/output (PE0) MTU input capture input/output compare output (TIOC0A) (Initial value)
300
Section 15 I/O Ports (I/O)
15.1 Overview
All the port pins are multiplexed as general input/output pins (general input pins in the case of port F) and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data.
15.2
Port A
Port A is an input/output port with the 15 pins shown in figure 15.1.
PA15 (I/O) / CK (output) PA14 (I/O) / RD (output) PA12 (I/O) / WRL (output) PA11 (I/O) / CS1 (output) PA10 (I/O) / CS0 (output) PA9 (I/O) / IRQ3 (input) Port A PA8 (I/O) / IRQ2 (input) PA7 (I/O) / CS3 (input) PA6 (I/O) / CS2 (input) PA5 (I/O) / SCK (I/O) PA4 (I/O) / TXD (output) PA3 (I/O) / RXD (input) PA2 (I/O) / IRQ0 (input) PA1 (I/O) PA0 (I/O)
Figure 15.1 Port A
301
15.2.1
Register Configuration
The port A registers are shown in table 15.1. Table 15.1 Port A Registers
Name Port A Data Register L Abbreviation PADRL R/W R/W Initial Value H'0000 Address H'FFFF8382 H'FFFF8383 Access Size 8, 16, 32
302
15.2.2
Port A Data Register L (PADRL)
Port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data. The bits of this register correspond to the various pins. When a pin functions as a general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PADRL is read the pin state, not the register value, is returned directly. If a value is written to PADRL, that value is written to PADRL but it does not affect the pin state. Table 15.2 summarizes the port A data register read/write operations. PADRL is initialized by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode.
Bit: 15 14 13 -- 0 R 5 PA5DR 0 R/W 12 11 10 9 PA9DR 0 R/W 1 PA1DR 0 R/W 8 PA8DR 0 R/W 0 PA0DR 0 R/W
PA15DR PA14DR Initial value: R/W: Bit: 0 R/W 7 PA7DR Initial value: R/W: 0 R/W 0 R/W 6 PA6DR 0 R/W
PA12DR PA11DR PA10DR 0 R/W 4 PA4DR 0 R/W 0 R/W 3 PA3DR 0 R/W 0 R/W 2 PA2DR 0 R/W
Table 15.2 Port A Data Register (PADR) Read/Write Operations
PAIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADR value PADR value Write Value is written to PADR, but does not affect pin state Value is written to PADR, but does not affect pin state Write value is output from pin Value is written to PADR, but does not affect pin state
303
15.3
Port B
Port A is an input/output port with the 10 pins shown in figure 15.2.
PB9 (I/O) / IRQ7 (input) / A21 (output) PB8 (I/O) / IRQ6 (input) A20 (output) / WAIT (input) PB7 (I/O) / A19 (output) PB6 (I/O) / A18 (output) Port B PB5 (I/O) PB4 (I/O) PB3 (I/O) / IRQ1 (input) PB2 (I/O) PB1 (I/O) / A17 (output) PB0 (I/O) / A16 (output)
Figure 15.2 Port B 15.3.1 Register Configuration
The port B registers are shown in table 15.3. Table 15.3 Port B Registers
Name Port B Data Register Abbreviation PBDR R/W R/W Initial Value H'0000 Address H'FFFF8390 H'FFFF8391 Access Size 8, 16, 32
304
15.3.2
Port B Data Register (PBDR)
The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. The bits of this register correspond to the various pins. When a pin functions as a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PBDR is read the pin state, not the register value, is returned directly. If a value is written to PBDR, that value is written to PBDR but it does not affect the pin state. Table 15.4 summarizes the port B data register read/write operations. PADR is initialized by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PB7DR Initial value: R/W: 0 R/W 14 -- 0 R 6 PB6DR 0 R/W 13 -- 0 R 5 PB5DR 0 R/W 12 -- 0 R 4 PB4DR 0 R/W 11 -- 0 R 3 PB3DR 0 R/W 10 -- 0 R 2 PB2DR 0 R/W 9 PB9DR 0 R/W 1 PB1DR 0 R/W 8 PB8DR 0 R/W 0 PB0DR 0 R/W
Table 15.4 Port B Data Register (PBDR) Read/Write Operations
PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Value is written to PBDR, but does not affect pin state Value is written to PBDR, but does not affect pin state Write value is output from pin Value is written to PBDR, but does not affect pin state
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15.4
Port C
Port C is an input/output port with the 16 pins shown in figure 15.3.
PC15 (I/O) /A15 (output) PC14 (I/O) /A14 (output) PC13 (I/O) /A13 (output) PC12 (I/O) /A12 (output) PC11 (I/O) /A11 (output) PC10 (I/O) /A10 (output) PC9 (I/O) /A9 (output) Port C PC8 (I/O) /A8 (output) PC7 (I/O) /A7 (output) PC6 (I/O) /A6 (output) PC5 (I/O) /A5 (output) PC4 (I/O) /A4 (output) PC3 (I/O) /A3 (output) PC2 (I/O) /A2 (output) PC1 (I/O) /A1 (output) PC0 (I/O) /A0 (output)
Figure 15.3 Port C 15.4.1 Register Configuration
The port C registers are shown in table 15.5. Table 15.5 Port C Registers
Name Port C Data Register Abbreviation PCDR R/W R/W Initial Value H'0000 Address H'FFFF8392 H'FFFF8393 Access Size 8, 16, 32
306
15.4.2
Port C Data Register (PCDR)
The port C data register (PCDR) is a 16-bit readable/writable register that stores port C data. The bits of this register correspond to the various pins. When a pin functions as a general output, if a value is written to PCDR, that value is output directly from the pin, and if PCDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PCDR is read the pin state, not the register value, is returned directly. If a value is written to PCDR, that value is written to PCDR but it does not affect the pin state. Table 15.6 summarizes the port C data register read/write operations. PCDR is initialized by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode.
Bit: 15 14 13 12 11 10 9 PC9DR 0 R/W 1 PC1DR 0 R/W 8 PC8DR 0 R/W 0 PC0DR 0 R/W
PC15DR PC14DR PC13DR PC12DR PC11DR PC10DR Initial value: R/W: Bit: 0 R/W 7 PC7DR Initial value: R/W: 0 R/W 0 R/W 6 PC6DR 0 R/W 0 R/W 5 PC5DR 0 R/W 0 R/W 4 PC4DR 0 R/W 0 R/W 3 PC3DR 0 R/W 0 R/W 2 PC2DR 0 R/W
Table 15.6 Port C Data Register (PCDR) Read/Write Operations
PCIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PCDR value PCDR value Write Value is written to PCDR, but does not affect pin state Value is written to PCDR, but does not affect pin state Write value is output from pin Value is written to PCDR, but does not affect pin state
307
15.5
Port D
Port D is an input/output port with the eight pins shown in figure 15.4.
PD7 (I/O) /D7 (I/O) PD6 (I/O)/D6 (I/O) PD5 (I/O)/D5 (I/O) Port D PD4 (I/O)/D4 (I/O) PD3 (I/O)/D3 (I/O) PD2 (I/O)/D2 (I/O) PD1 (I/O)/D1 (I/O) PD0 (I/O)/D0 (I/O)
Figure 15.4 Port D 15.5.1 Register Configuration
The port D registers are shown in table 15.7. Table 15.7 Port D Registers
Name Port D Data Register L Abbreviation PDDRL R/W R/W Initial Value H'0000 Address H'FFFF83A2 H'FFFF83A3 Access Size 8, 16, 32
308
15.5.2
Port D Data Register L (PDDRL)
Port D data register L (PDDRL) is a 16-bit readable/writable register that stores port D data. The bits of this register correspond to the various pins. When a pin functions as a general output, if a value is written to PDDRL, that value is output directly from the pin, and if PDDRL is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PDDRL is read the pin state, not the register value, is returned directly. If a value is written to PDDRL, that value is written to PDDRL but it does not affect the pin state. Table 15.8 summarizes the port D data register read/write operations. PDDRL is initialized by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PD7DR Initial value: R/W: 0 R/W 14 -- 0 R 6 PD6DR 0 R/W 13 -- 0 R 5 PD5DR 0 R/W 12 -- 0 R 4 PD4DR 0 R/W 11 -- 0 R 3 PD3DR 0 R/W 10 -- 0 R 2 PD2DR 0 R/W 9 -- 0 R 1 PD1DR 0 R/W 8 -- 0 R 0 PD0DR 0 R/W
Table 15.8 Port D Data Register (PDDR) Read/Write Operations
PDIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PDDR value PDDR value Write Value is written to PDDR, but does not affect pin state Value is written to PDDR, but does not affect pin state Write value is output from pin Value is written to PDDR, but does not affect pin state
309
15.6
Port E
Port E is an input/output port with the 13 pins shown in figure 15.5.
PE14 (I/O) PE13 (I/O) PE12 (I/O) PE11 (I/O) PE10 (I/O) Port E PE9 (I/O) PE8 (I/O) PE7 (I/O) /TIOC2B (I/O) PE6 (I/O) /TIOC2A (I/O) PE5 (I/O) /TIOC1B (I/O) PE4 (I/O) /TIOC1A (I/O) PE2 (I/O) /TIOC0C (I/O) PE0 (I/O) /TIOC0A (I/O)
Figure 15.5 Port E 15.6.1 Register Configuration
The port E registers are shown in table 15.9. Table 15.9 Port E Registers
Name Port E Data Register Abbreviation PEDR R/W R/W Initial Value H'0000 Address H'FFFF83B0 H'FFFF83B1 Access Size 8, 16, 32
310
15.6.2
Port E Data Register (PEDR)
The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. The bits of this register correspond to the various pins. When a pin functions as a general output, if a value is written to PEDR, that value is output directly from the pin, and if PEDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PEDR is read the pin state, not the register value, is returned directly. If a value is written to PEDR, that value is written to PEDR but it does not affect the pin state. Table 15.10 summarizes the port E data register read/write operations. PEDR is initialized by an external power-on reset. However, it is not initialized by a WDT reset, in standby mode, or in sleep mode.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PE7DR Initial value: R/W: 0 R/W 14 13 12 11 10 9 PE9DR 0 R/W 1 -- 0 R 8 PE8DR 0 R/W 0 PE0DR 0 R/W
PE14DR PE13DR PE12DR PE11DR PE10DR 0 R/W 6 PE6DR 0 R/W 0 R/W 5 PE5DR 0 R/W 0 R/W 4 PE4DR 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 PE2DR 0 R/W
Table 15.10 Port E Data Register (PEDR) Read/Write Operations
PEIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PEDR value PEDR value Write Value is written to PEDR, but does not affect pin state Value is written to PEDR, but does not affect pin state Write value is output from pin Value is written to PEDR, but does not affect pin state
311
15.7
Port F
Port F is an input port with the eight pins shown in figure 15.6.
PF7 (input) /AN7 (input) PF6 (input) /AN6 (input) PF5 (input) /AN5 (input) Port F PF4 (input) /AN4 (input) PF3 (input) /AN3 (input) PF2 (input) /AN2 (input) PF1 (input) /AN1 (input) PF0 (input) /AN0 (input)
Figure 15.6 Port F 15.7.1 Register Configuration
The port F registers are shown in table 15.11. Table 15.11 Port F Registers
Name Abbreviation R/W Initial Value Address Access Size
Port F Data Register PFDR
R/W Depends on external pins H'FFFF83B3 8
312
15.7.2
Port E Data Register (PFDR)
The port F data register (PFDR) is an 8-bit read-only register that stores port F data. The bits of this register correspond to the various pins. Writes to these bits are ignored, and do not affect the pin states. When these bits are read the pin state, not the register value, is returned directly. However, 1 is returned while A/D converter analog input is being sampled. Table 15.12 summarizes the port E data register read/write operations. PFDR is not initialized by a power-on reset, in standby mode, or in sleep mode. (The bits always reflect the pin states.)
Bit: 7 PF7DR Initial value: R/W: * R 6 PF6DR * R 5 PF5DR * R 4 PF4DR * R 3 PF3DR * R 2 PF2DR * R 1 PF1DR * R 0 PF0DR * R
Note: * These values depend on the pin state when the initial value is read.
Table 15.12 Port F Data Register (PFDR) Read/Write Operations
Pin Function Input Pin state General input ANn ANn: Analog input Read Pin state is read 1 is read Write Ignored (does not affect pin state) Ignored (does not affect pin state)
313
314
Section 16 160 kB Flash Memory (F-ZTAT)
16.1 Features
The SH7018 has 160 kbytes of on-chip flash memory. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. Erasing the entire memory requires erasure of each block in turn. Block erasing can be performed as required on 4 kB, 32 kB, and 64 kB blocks. * Programming/erase times The flash memory programming time is 25 ms (typ.) for simultaneous 128-byte programming, equivalent to 195 s (typ.) per byte, and the erase time is 10 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode, the SH7018's bit rate can be automatically adjusted to match the transfer bit rate of the host. Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. Protect modes There are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations. Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode.
*
*
*
*
315
16.2
16.2.1
Overview
Block Diagram
Internal address bus
Internal data bus (32 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER Bus interface/controller Operating mode FWP pin Mode pin
Flash memory (160 kB)
Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER:
Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register
Figure 16.1 Block Diagram of Flash Memory
316
16.2.2
Mode Transitions
When the mode pins and the FWP pin are set in the reset state and a reset-start is executed, the SH7018 enters one of the operating modes shown in figure 16.2. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
MD1 = 1, FWP = 1 *1 User mode MD1 = 1, FWP = 0 FWP = 0 FWP = 1 RES = 0
Reset state
RES = 0 RES = 0 MD1 = 0, FWP = 0 *1 RES = 0 Programmer mode *2
User program mode
Boot mode On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 1, MD1 = 0, MD2 = 1, MD3 = 1
Figure 16.2 Flash Memory Mode Transitions
317
16.2.3
On-Board Programming Modes
Boot Mode Figure 16.3 illustrates overwrite operation in the boot mode. For more information on the boot mode, see 16.6.1, Boot Mode.
1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the SH7018 (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area.
Host
; ;
Host Programming control program New application program New application program SH7018 SH7018 Boot program SCI1 Boot program SCI1 Flash memory RAM Flash memory RAM
Programming control program
Application program (old version)
Application program (old version)
Boot program area
3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks.
Host
4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory.
Host
New application program
SH7018
SH7018
Boot program
SCI1
Boot program
SCI1
Flash memory
RAM
Flash memory
RAM
Programming control program
Programming control program
Flash memory erase
Boot program area
New application program
Boot program area
Program execution state
Figure 16.3 Overwrite Operation in the Boot Mode
318
User Program Mode Figure 16.4 illustrates overwrite operation in the user program mode. For more information on the user program mode, see 16.6.2, User Program Mode.
1. Initial state The FWP assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory.
Host Programming/ erase control program New application program SH7018 Boot program Flash memory
FWP assessment program
2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM.
Host
New application program SH7018 SCI1 RAM Boot program Flash memory
FWP assessment program
SCI1 RAM
Programming/ erase control program
;;
Application program (old version) Application program (old version)
Transfer program
Transfer program
3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units.
Host
4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks.
Host
New application program
SH7018
SH7018
Boot program
SCI1
Boot program
SCI1
Flash memory
RAM
Flash memory
RAM
FWP assessment program
Programming/ erase control program
FWP assessment program
Programming/ erase control program
Transfer program
Transfer program
Flash memory erase
New application program
Program execution state
Figure 16.4 Example of Overwrite Operation in the User Program Mode
319
16.2.4
Flash Memory Emulation in RAM
Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. * User Mode * User Program Mode
SCI1
Flash memory
RAM
Application program Execution state Overlap RAM (emulation is performed on data written in RAM)
Emulation block
Figure 16.5 RAM Emulation (RAM Overlap) When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
320
* User Program Mode
SCI1
Flash memory
RAM Programming control program execution state
Application program Overlap RAM (programming data)
Programming data
Figure 16.6 RAM Emulation (Flash Memory Overwrite) 16.2.5 Differences between Boot Mode and User Program Mode
Boot Mode Entire memory erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3)
(1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm.
321
16.2.6
Block Configuration
The flash memory is divided into eight 4 kB blocks, two 32 kB blocks, and one 64 kB block. The data in flash memory can be deleted one block at a time in the user program mode.
Address H'00000
4 kB 4 kB 4 kB 4 kB 4 kB 4 kB 4 kB 4 kB
160 kB
32 kB
64 kB
32 kB
Address H'27FFF
Figure 16.7 Block Configuration of Area to Be Deleted
16.3
Pin Configuration
The flash memory is controlled by means of the pins shown in table 16.1. Table 16.1 Flash Memory Pins
Pin Name Power-on reset Flash memory write protect Mode 3 Mode 2 Mode 1 Mode 0 Transmit data Receive data Abbreviation RES FWP MD3 MD2 MD1 MD0 TxD RxD I/O Input Input Input Input Input Input Output Input Function Power-on reset Flash program/erase protection by hardware Sets SH7018 operating mode Sets SH7018 operating mode Sets SH7018 operating mode Sets SH7018 operating mode Serial transmit data output Serial receive data input
322
16.4
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 16.2. Table 16.2 Flash Memory Registers
Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER R/W R/W* R R/W*1 R/W* R/W
1 1
Initial Value H'00* H'00 H'00* 3 H'00*
3 2
Address H'FFFF8580 H'FFFF8581 H'FFFF8582 H'FFFF8583 H'FFFF8628
Access Size 8 8 8 8 8, 16, 32
H'0000
Notes: 1. Writes are disabled when the FWE bit is set to 1 in FLMCR1. 2. When a low level is input to the FWP pin, the initial value is H'80. 3. When a high level is input to the FWP pin, or if a low level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 4. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit register. 5. Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a longword access. 6. When a longword write is performed on RAMER, 0 must always be written to the lower word (address H'FFFF8630). Operation is not guaranteed if any other value is written.
323
16.5
16.5.1
Register Descriptions
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a power-on reset, and in standby mode. Its initial value is H'80 when a low level is input to the FWP pin, and H'00 when a high level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to bits SWE, ESU, PSU, EV, and PV are enabled only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1.
Bit: 7 FWE Initial value: R/W: 1/0 R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W
* Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing.
Bit 7: FWE 0 1 Description When a high level is input to the FWP pin (hardware-protected state) When a low level is input to the FWP pin (Initial value)
* Bit 6--Software Write Enable Bit (SWE): Enables or disables the flash memory. This bit should be set before setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 2 to 0. The flash memory cannot be read when SWE is set to 1, except in the program verify/erase verify mode.
Bit 6: SWE 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value)
324
* Bit 5--Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 5: ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value)
* Bit 4--Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 4: PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value)
* Bit 3--Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time.
Bit 3: EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value)
* Bit 2--Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2: PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value)
325
* Bit 1--Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.
Bit 1: E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU1 = 1 (Initial value)
* Bit 0--Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time.
Bit 0: P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 (Initial value)
326
16.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection). FLMCR2 is initialized to H'00 by a power-on reset. When on-chip flash memory is disabled, a read will return H'00.
Bit: 7 FLER Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
* Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Bit 7: FLER 0 Description Flash memory is operating normally. Flash memory program/erase protection (error protection) is disabled. [Clearing condition] Power-on reset 1 An error has occurred during flash memory programming/erasing. Flash memory program/erase protection (error protection) is enabled. [Setting condition] See section 16.8.3, Error Protection. (Initial value)
* Bits 6 to 0--Reserved: These bits are always read as 0. The write value should always be 0.
327
16.5.3
Erase Block Register 1 (EBR1)
EBR1 is an 8-bit readable/writable register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in standby mode, when a high level is input to the FWP pin, and when a low level is input to the FWP pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are eraseprotected. As with EBR2, set only one bit of EBR1 (more than one bit cannot be set). If two or more bits are set, writes to the ESU and E bits are invalid. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 16.3.
Bit: 7 EB7 Initial value: R/W: 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W
16.5.4
Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset and in standby mode, when a high level is input to the FWP pin, and when a low level is input to the FWP pin and the SWE bit of FLMCR1 is not set. When a bit in EBR2 is set to 1, the corresponding block can be erased. The other blocks are eraseprotected. If the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 16.3.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W
* Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0.
328
Table 16.3 Flash Memory Erase Blocks
Block (Size) EB0 (4 kB) EB1 (4 kB) EB2 (4 kB) EB3 (4 kB) EB4 (4 kB) EB5 (4 kB) EB6 (4 kB) EB7 (4 kB) EB8 (32 kB) EB9 (64 kB) EB10 (32 kB) Address H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'027FFF
16.5.5
RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset. It is not initialized in standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 16.4. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 RAMS 0 R/W 9 -- 0 R 1 RAM1 0 R/W 8 -- 0 R 0 RAM0 0 R/W
* Bits 15 to 3--Reserved: These bits are always read as 0. The write value should always be 0.
329
* Bit 2--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 2: RAMS 0 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value)
* Bits 1 and 0--Flash Memory Area Selection (RAM1, RAM0): These bits are used together with bit 2 to select the flash memory area to be overlapped with RAM. For each block, only the first 1 kB of addresses can be overlapped. (See table 16.4.) Table 16.4 Flash Memory Area Divisions
Addresses H'FFF800 to H'FFFBFF H'004000 to H'0043FF H'005000 to H'0053FF H'006000 to H'0063FF H'007000 to H'0073FF Block Name RAM area 1 kB EB4 (1 kB) EB5 (1 kB) EB6 (1 kB) EB7 (1 kB) RAMS 0 1 1 1 1 RAM1 * 0 0 1 1 RAM0 * 0 1 0 1
16.6
On-Board Programming Modes
When pins are set to on-board programming mode and a power-on reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 16.5. For a diagram of the transitions to the various flash memory modes, see figure 16.2. Table 16.5 Setting On-Board Programming Modes
Mode Boot mode User program mode FWP 0 0 MD3 0 0 MD2 0 0 MD1 0 1 MD0 0 0
330
16.6.1
Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI1 to be used is set to channel asynchronous mode. When a reset-start is executed after the SH7018 pins have been set to boot mode in the power-on reset state, the boot program built into the SH7018 is started and the programming control program prepared in the host is serially transmitted to the SH7018 via SCI1 (RxD, TxD). In the SH7018, the programming control program received via SCI1 is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 16.8, and the boot mode execution procedure in figure 16.9.
SH7018
Flash memory
Host
Write data reception Verify data transmission
RXD SCI1 TXD On-chip RAM
Figure 16.8 System Configuration in Boot Mode
331
Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate SH7018 measures low period of H'00 data transmitted by host SH7018 calculates bit rate and sets value in bit rate register After bit rate adjustment, SH7018 transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, SH7018 transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte SH7018 transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units SH7018 transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, SH7018 transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM
n+1n
n = N?
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted.
Figure 16.9 Boot Mode Execution Procedure
332
Automatic SCI Bit Rate Adjustment
Start bit Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
Low period (9 bits) measured (H'00 data)
High period (1 or more bits)
When boot mode is initiated, the SH7018 measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7018 calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7018. If reception cannot be performed normally, initiate boot mode again (power-on reset), and repeat the above operations. Depending on the host's transmission bit rate and the SH7018's system clock frequency, there will be a discrepancy between the bit rates of the host and the SH7018. To ensure correct SCI operation, the host's transfer bit rate should be set to 4800bps, 9600bps. Table 16.6 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the SH7018 bit rate is possible. The boot program should be executed within this system clock range. Table 16.6 System Clock Frequencies for which Automatic Adjustment of SH7018 Bit Rate is Possible
Host Bit Rate 19200 bps 9600 bps 4800 bps System Clock Frequency for which Automatic Adjustment of SH7018 Bit Rate is Possible 16 to 20 MHz 8 to 20 MHz 4 to 20 MHz
333
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 16.10. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host.
H'FFFFF000 Programming control program area (2 kbytes) H'FFFFF800 Boot program area (2 kbytes) H'FFFFFFFF
Figure 16.10 RAM Areas in Boot Mode Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program.
334
16.6.2
User Program Mode
After setting FWP, the user should branch to, and execute, the previously prepared programming/erase control program. As the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip RAM or external memory. Use the following procedure (figure 16.11) to execute the programming control program that writes to flash memory (when transferred to RAM).
1
Write FWP assessment program and transfer program
2
FWP = 0 (user program mode)
3
Transfer programming/erase control program to RAM
4
Execute programming/ erase control program in RAM (flash memory rewriting)
5
Execute user application program
Figure 16.11 User Program Mode Execution Procedure Note: When programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. Memory cells may not operate normally if overprogrammed or overerased due to program runaway.
335
16.7
Programming/Erasing Flash Memory
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program (programming control program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, a low level is input to the FWP pin (programming/erasing will not be executed if a high level is input to the FWP pin). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. 16.7.1 Program Mode
Follow the procedure shown in the program/program-verify flowchart in figure 16.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. Following the elapse of 1 s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program address (the lower 8 bits of the first address written to must be H'00, or H'80). The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of 50 s or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. For the write time, refer to the table accompanying the Program/ProgramVerify Flowchart.
336
16.7.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSUn bit is cleared at least 5 s later). The watchdog timer is cleared after the elapse of 5 s or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of 4 s or more. When the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. Wait at least 2 s after the dummy write before performing this read operation. Next, the written data is compared with the verify data, and reprogram data is computed (see figure 16.12) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program verify mode, wait for at least 2 s, clear the SWE bit in FLMCR1, then wait for at least 100 s. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than 1,000 times on the same bits.
337
Write pulse application subroutine Sub-routine write pulse Enable WDT Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait 10 s, 30 s, or 200 s Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s Disable WDT End sub *5
Start of programming Start Set SWE bit in FLMCR1 Wait 1 s Store 128-byte program data in program data storage area and reprogram data storage area *4 n=1 m=0
Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed.
Write 128-byte data in reprogram data storage *1 area in RAM consecutively to flash memory Sub-routine-call Write pulse See Note 6 for pulse width 30 s or 200 s Set PV bit in FLMCR1 Wait 4 s H'FF dummy write to verify address Increment address Wait 2 s Read verify data *2 NG m=1 NG nn+1
Note 6: Write Pulse Width Number of Writes n Write Time (z) (sec) 1 30 2 30 3 30 4 30 5 30 6 30 7 200 8 200 9 200 10 200 11 200 12 200 13 200 . . . . . . 998 200 999 200 1000 200 Note: Use a 10 s write pulse for additional programming.
Program data = verify data? OK 6 n? OK Additional program data computation
Transfer additional program data to additional program data storage area Reprogram data computation Transfer reprogram data to reprogram data storage area
*4 *3 *4
NG
128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait 2 s
RAM Program data storage area (128 bytes) Reprogram data storage area (128 bytes) Additional program data storage area (128 kbytes)
6 n?
NG
OK Write 128-byte data in additional program data storage area in RAM consecutively to flash memory *1 Additional write pulse 10 s NG n 1000? OK Clear SWE bit in FLMCR1 Wait 100 s Programming failure NG Reprogram
m = 0? OK Clear SWE bit in FLMCR1 Wait 100 s End of programming
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 32-bit (longword) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in RAM. The reprogram and additional program data contents are modified as programming proceeds. 5. The write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for the pulse widths. When writing of additional program data is executed, a 10 s write pulse should be applied. Reprogram data X means reprogram data when the write pulse is applied. Reprogram Data Computation Chart Verify Data (V) Original Data (D) 0 0 1 0 1 1 Reprogram Data (X) 1 0 1 1 Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Comments Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed
Additional Program Data Computation Chart Verify Data (V) Additional Program Data (Y) Reprogram Data (X') 0 0 0 1 1 0 1 1 1 1
Figure 16.12 Program/Program-Verify Flowchart
338
Sample 128-Byte Programming Program: The wait time set values (number of loops) are for the case where f = 20 MHz. For other frequencies, the set value is given by {wait time (s) x f (MHz) / 4}. Registers Used R11 (input): R12 (input): R13 (output): R0-10, 14:
FLMCR1 OK NG WAIT_X WAIT_Y WAIT_Z1 WAIT_Z5 WAIT_ZA WAIT_A WAIT_B WAIT_C WAIT_D WAIT_E WAIT_F WDT_TCSR .EQU WDT_1m SWESET PSUSET PSET PCLEAR PSUCLEAR .EQU PVSET PVCLEAR SWECLEAR .EQU MAXVERIFY ; FLASHPROGRAM MOV MOV.L .EQU $ ; Save program data to ; work area 339
Program data storage address Programming destination address OK (normal) or NG (error) Work registers
.EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU H'80 H'0 H'1 5 250 150 1000 50 25 25 20 10 10 500 ; 1 s ; 50 s ; 30 s (1st to 6th time) ; 200 s (7th to 1000th time) ; 10 s (Additional write) ; 5 s ; 5 s ; 4 s ; 2 s ; 2 s ; 100 s
H'FFFF8610 .EQU .EQU .EQU .EQU .EQU H'40 .EQU .EQU H'00 .EQU H'A57A H'40 H'50 H'51 H'50 ; B'01000000 H'44 H'40 ; B'00000000 1000 ; B'01000100 ; B'01000000 ; B'01000000 ; B'01010000 ; B'01010001 ; B'01010000
R11,R3 #RDATABUFF,R0
MOV.L MOV COPY_LOOP1 MOV.L MOV.L MOV.L ADD ADD DT BF MOV.L LDC ; MOV.L MOV MOV.B WAIT_1 DT BF ; MOV PROGRAM_LOOP MOV MOV.L MOV.L MOV WRITE_LOOP1 MOV.B MOV.B ADD DT BF ; MOV.L MOV.L MOV.W ; MOV.L 340
#ADATABUFF,R2 #32,R6 .EQU $
@R3+,R1 R1,@R0 R1,@R2 #4,R0 #4,R2 R6 COPY_LOOP1 #H'FFFF8500,R0 R0,GBR ; Initialize GBR
#WAIT_X,R2 #SWESET,R0 R0,@(FLMCR1,GBR) R2 WAIT_1 ; Initialize N (R14) to 1 ; Initialize M (R5) to 0 ; Write 128-byte data consecutively ; Set SWE ; Wait 1 s
#1,R14 .EQU #0,R5 #128,R2 #RDATABUFF,R3 R12,R6 .EQU $ $
@R3+,R1 R1,@R6 #1,R6 R2 WRITE_LOOP1 ; Enable WDT ; 1.6 ms cycle
#WDT_TCSR,R0 #WDT_1m,R1 R1,@R0
#WAIT_Y,R2
MOV MOV.B WAIT_2 DT BF ; MOV.L MOV CMP/GE BT MOV.L UNDER7 MOV MOV.B WAIT_3 DT BF ; MOV.L MOV MOV.B WAIT_4 DT BF ; MOV.L MOV MOV.B WAIT_5 DT BF ; MOV.L MOV.W MOV.W ; MOV.L MOV MOV.B WAIT_6 DT BF ;
#PSUSET,R0 R0,@(FLMCR1,GBR) R2 WAIT_2
; Set PSU ; Wait 50 s
#WAIT_Z1,R2 #6,R3 R14,R3 UNDER7 #WAIT_Z5,R2 #PSET,R0 R0,@(FLMCR1,GBR) R2 WAIT_3
; 1st to 6th time
; 7th to 1000th time ; Set P ; Wait 30 s or 200 s
#WAIT_A,R2 #PCLEAR,R0 R0,@(FLMCR1,GBR) R2 WAIT_4 ; Wait 5 s ; Clear P
#WAIT_B,R2 #PSUCLEAR,R0 R0,@(FLMCR1,GBR) R2 WAIT_5 ; Disable WDT ; Wait 5 s ; Clear PSU
#WDT_TCSR,R0 #H'A55F,R1 R1,@R0
#WAIT_C,R2 #PVSET,R0 R0,@(FLMCR1,GBR) R2 WAIT_6 ; Wait 4 s ; Set PV
341
MOV.L MOV.L MOV MOV MOV MOV.L ; VERIFYLOOP MOV.L MOV.L MOV.L WAIT_7 DT BF ; MOV.L MOV.L CMP/EQ BT MOV ; VERIFY_OK MOV CMP/GE BF MOV.L OR MOV.L ; NO_ADWRT .EQU MOV.L NOT OR MOV.L ; ADD ADD DT 342
#ADATABUFF,R9 #RDATABUFF,R7 R11,R1 R12,R3 #32,R6 #H'FFFFFFFF,R4
.EQU
$ ; Write H'FF to verify address
; Additional program data RAM (ADATABUFF) initialization
R4,@R3 R4,@R9 #WAIT_D,R2 R2 WAIT_7
; Wait 2 s
@R3+,R2 @R1+,R0 R2,R0 VERIFY_OK #1,R5
; Read verify data ; Read program data (source data) ; Verify check ; If verify NG, assign 1 to M
.EQU #6,R8
$ ; 6 or more writes?
R14,R8 NO_ADWRT @R7,R10 R2,R10 R10,@R9 ; Read reprogram data ; Additional program data operation ; Store in additional program data RAM (ADATABUFF)
$ R4,@R7 R2,R2 R2,R0 R0,@R7 ; Store in reprogram data RAM (RDATABUFF) ; Reprogram data RAM (RDATABUFF) initialization ; Reprogram data computation
#4,R7 #4,R9 R6
BF ; MOV.L MOV MOV.B WAIT_8 DT BF ; MOV CMP/GE BF ; MOV.L MOV.L MOV WRITE_LOOP2 MOV.B MOV.B ADD DT BF ; MOV.L MOV.L MOV.W ; MOV.L MOV MOV.B WAIT_9 DT BF ; MOV.L MOV MOV.B WAIT_10 DT BF
VERIFYLOOP
#WAIT_E,R2 #PVCLEAR,R0 R0,@(FLMCR1,GBR) R2 WAIT_8 ; 6 or more writes? ; Wait 2 s ; Clear PV
#6,R8 R14,R8 NO_ADWRT2
#128,R2 #ADATABUFF,R3 R12,R6 .EQU $
; Consecutively write 128-byte date to ; additional program data RAM (ADATABUFF)
@R3+,R1 R1,@R6 #1,R6 R2 WRITE_LOOP2 ; Enable WDT ; 1.6 ms cycle
#WDT_TCSR,R0 #WDT_1m,R1 R1,@R0
#WAIT_Y,R2 #PSUSET,R0 R0,@(FLMCR1,GBR) R2 WAIT_9 ; 10 s additional write ; Set P ; Wait 10 s ; Wait 50 s ; Set PSU
#WAIT_ZA,R2 #PSET,R0 R0,@(FLMCR1,GBR) R2 WAIT_10
343
; MOV.L MOV MOV.B WAIT_11 DT BF ; MOV.L MOV MOV.B WAIT_12 DT BF ; MOV.L MOV.W MOV.W ; NO_ADWRT2 CMP/PL BF ADD MOV MOV.L CMP/GT BF ; BRA NOP ; PROGRAM_OK MOV PROGRAM_END MOV MOV.B ; MOV.L WAIT_13 DT 344 #WAIT_F,R2 R2 ; Wait 100 s .EQU $ ; Move OK (return value) to R13 ; Clear SWE PROGRAM_LOOP .EQU R5 PROGRAM_OK #1,R14 #NG,R13 #MAXVERIFY,R3 R14,R3 PROGRAM_END ; Move NG (return value) to R13 ; If N 1000, programming error $ ; If M = 0, end of programming #WDT_TCSR,R0 #H'A55F,R1 R1,@R0 ; Disable WDT #WAIT_B,R2 #PSUCLEAR,R0 R0,@(FLMCR1,GBR) R2 WAIT_12 ; Wait 5 s ; Clear PSU #WAIT_A,R2 #PCLEAR,R0 R0,@(FLMCR1,GBR) R2 WAIT_11 ; Wait 5 s ; Clear P
#OK,R13 .EQU $
#SWECLEAR,R0 R0,@(FLMCR1,GBR)
BF ; RTS NOP ; ADATABUFF RDATABUFF
WAIT_13
.RES.B 128 .RES.B 128
; Additional programming RAM area ; Reprogramming RAM area
16.7.3
Erase Mode
Flash memory is erased one block at a time using the method shown in figure 16.13, Erase/EraseVerify Flowchart (Single-Block Erasure). To perform data or program erasure, set the 1-bit flash memory area to be erased in erase block register 1 (EBR1) and erase block register 2 (EBR2) at least 1 s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of 100 s or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed 10 ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all "0") is not necessary before starting the erase procedure.
345
16.7.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit is cleared at least 10 s later), the watchdog timer is cleared after the elapse of 10 s or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of 6 s or more. When the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. Wait at least 2 s after the dummy write before performing this read operation. If the read data has been erased (all "1"), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/eraseverify sequence in the same way. However, ensure that the erase/erase-verify sequence is not repeated more than 100 times. When verification is completed, exit erase-verify mode, and wait for at least 4 s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, set 1 bit for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way.
346
Start
*1
Set SWE bit in FLMCR1 Wait 1 s n=1 Set EBR1/EBR2 Enable WDT Set ESU bit in FLMCR1 Wait 100 s Set E bit in FLMCR1 Wait 10 ms Clear E bit in FLMCR1 Wait 10 s Clear ESU bit in FLMCR1 Wait 10 s Disable WDT Set EV bit in FLMCR1 Wait 6 s Set block start address to verify address Erase halted nn+1 Start of erase
*3
H'FF dummy write to verify address Wait 2 s Increment address Read verify data Verify data = all "1"? Yes No Last address of block? Yes Clear EV bit in FLMCR1 Wait 4 s No
*4 *2
No
Clear EV bit in FLMCR1 Wait 4 s No
Erasing of all erase blocks completed? Yes
n 100? Yes Clear SWE bit in FLMCR1 Wait 100 s Erase failure
Clear SWE bit in FLMCR1 Wait 100 s End of erase Notes: 1. 2. 3. 4.
Preprogramming (setting erase block data to all "0") is not necessary. Verify data is read in 32-bit (longword) units. Set only one bit in the erase block register (EBR). Two or more bits must not be set. Erasing is performed in block units. For a multiple-block erase, the individual blocks must be erased sequentially.
Figure 16.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
347
Sample Single-Block Erase Program: The wait time set values (number of loops) are for the case where f = 20 MHz. For other frequencies, the set value is given by {wait time (s) x f (MHz) / 4}. Registers Used R5 (input): Memory block table pointer R7 (output): OK (normal) or NG (error) R0-3, 6, 8-9: Work registers
FLMCR1 EBR1 OK NG EWait_X EWait_Y EWait_Z EWait_a EWait_b EWait_c EWait_d EWait_e EWait_f WDT_TCSR WDT_6m SWESET ESUSET ESET ECLEAR ESUCLEAR EVSET EVCLEAR SWECLEAR MAXErase ; FlashErase MOV.L LDC MOV.L ; 348 .EQU #H'FFFF8500,R0 R0,GBR #1,R2 ; Initialize GBR $ .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU EQU EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU H'80 H'02 H'0 H'1 5 500 50000 50 50 30 10 20 500 H'FFFF8610 H'A57C B'01000000 B'00100000 B'00000010 B'11111101 B'11011111 B'00001000 B'11110111 B'10111111 100
MOV,L MOV.L OR.B EWait_1 SUBC BF ; MOV.L ; MOV.W MOV.W MOV.L
#EWait_X,R3 #FLMCR1,R0 #SWESET,@(R0,GBR) R2,R3 EWait_1 ; Initialize n (R9) to 0 ; Set SWE ; Wait 1 s
#0,R9
@(6,R5),R0 R0,@(EBR1,GBR) @R5,R6 ; Erase memory block (EBR1/2) setting ; Erase memory block start address ; R6 setting
; EraseLoop MOV.L MOV.W MOV.W MOV.L MOV.L OR.B EWait_2 SUBC BF ; MOV.L OR.B EWait_3 SUBC BF ; MOV.L AND.B EWait_4 SUBC BF ; MOV.L AND.B EWait_5 SUBC BF #EWait_b,R3 #ESUCLEAR,@(R0,GBR) R2,R3 EWait_5 349 ; Clear ESU ; Wait 10 s #EWait_a,R3 #ECLEAR,@(R0,GBR) R2,R3 EWait_4 ; Clear E ; Wait 10 s #EWait_Z,R3 #ESET,@(R0,GBR) R2,R3 EWait_3 ; Set E ; Wait 10 ms .EQU #WDT_TCSR,R1 #WDT_6m,R3 R3,@R1 #EWait_Y,R3 #FLMCR1,R0 #ESUSET,@(R0,GBR) R2,R3 EWait_2 ; Set ESU ; Wait 100 s $ ; Enable WDT ; 6.5 ms cycle
; MOV.L MOV.W MOV.W ; MOV.L OR.B EWait_6 SUBC BF ; BlockVerify_1 MOV.L MOV.L MOV.L EWait_7 SUBC BF ; MOV.L CMP/EQ BF MOV.L CMP/EQ BF MOV.L AND.B EWait_8 SUBC BF ; MOV.L BRA NOP ; BlockVerify_NG ADD.L ADD.L MOV.L AND.B 350 .EQU #1,R9 #-4,R6 #EWait_e,R3 #EVCLEAR,@(R0,GBR) ; Clear EV $ ; If verify NG, assign n+1 to n ; Next verify address #OK,R7 FlashErase_end ; Move OK (return value) to R7 ; Verify OK @R6+,R1 R8,R1 BlockVerify_NG @(8,R5),R7 R6,R7 BlockVerify_1 #EWait_e,R3 #EVCLEAR,@(R0,GBR) R2,R3 EWait_8 ; Clear EV ; Wait 4 s ; Check for last address of memory block ; Read verify data .EQU #H'FFFFFFFF,R8 R8,@R6 #EWait_d,R3 R2,R3 EWait_7 ; Wait 2 s ; H'FF dummy write $ ; Erase-verify #EWait_c,R3 #EVSET,@(R0,GBR) R2,R3 EWait_6 ; Set EV ; Wait 6 s #WDT_TCSR,R1 #H'A55F,R3 R3,@R1 ; Disable WDT
EWait_9
SUBC BF
R2,R3 EWait_9
; Wait 4 s
; MOV.L CMP/EQ BF MOV.L FlashErase_end MOV.L AND.B MOV.L Ewait_10 SUBC BF ; RTS NOP ; ;Memory block table .ALIGN Flash_BlockData EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 EB8 EB9 EB10 Dummy .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L .DATA.L Memory block start address: EBR value 4 .EQU $ #MAXErase,R7 R7,R9 EraseLoop #NG,R7 .EQU #FLMCR1,R0 #SWECLEAR,@(R0,GBR) #Ewait_f,R3 R2,R3 Ewait_10 ; Wait 100 s ; Clear SWE $ ; Move NG (return value) to R7 ; If N > 100, erase error
H'00000000,H'00000100 H'00001000,H'00000200 H'00002000,H'00000400 H'00003000,H'00000800 H'00004000,H'00001000 H'00005000,H'00002000 H'00006000,H'00004000 H'00007000,H'00008000 H'00008000,H'00000001 H'00010000,H'00000002 H'00020000,H'00000004 H'00028000
351
16.7.5
Wait Time Widths in Programming/Erasing
Various wait time widths in the program/erase control program provided by the user should be within the specifications shown below. Table 16.7 Programming/Erasing-Related Wait Width Specifications
Flow Section Programmingrelated Item Wait time after PSU bit setting Wait time after P bit setting (10 s) Wait time after P bit setting (30 s) Wait time after P bit setting (200 s) Wait time after P bit clearing Wait time after PSU bit clearing Wait time after PV bit setting Wait time after dummy write Wait time after PV bit clearing Erase-related Wait time after ESU bit setting Wait time after E bit setting Wait time after E bit clearing Wait time after ESU bit clearing Wait time after EV bit setting Wait time after dummy write Wait time after EV bit clearing Other (common) Wait time after SWE bit setting Wait time after SWE bit clearing Symbol tspsu tsp10 Min 50 8 Typ 50 10 Max -- 12 Unit s s Additionalprogramming time wait Programming time wait Programming time wait Notes
tsp30 tsp200 tcp tcpsu tspv tspvr tcpv tsesu tse tce tcesu tsev tsevr tcev tsswe tcswe
28 198 5 5 4 2 2 100 10 10 10 6 2 4 1 100
30 200 5 5 4 2 2 100 10 10 10 6 2 4 1 100
32 202 -- -- -- -- -- -- 100 -- -- -- -- -- -- --
s s s s s s s s ms s s s s s s s
Erase time wait
352
16.8
Protection
There are two kinds of flash memory program/erase protection, hardware protection and software protection. 16.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, EBR1, and EBR2 settings are retained in the error-protected state. (See table 16.8.) Table 16.8 Hardware Protection
Functions Item FWP pin protection Description * When a high level is input to the FWP pin, FLMCR1, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a power-on reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Program Yes Erase Yes
Reset/standby protection
*
Yes
Yes
*
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16.8.2
Software Protection
Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), the RAMS bit in erase block register 1 (EBR1), erase block register 2 (EBR2), and RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 16.9.) Table 16.9 Software Protection
Functions Item SWE bit protection Description * Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection * Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. -- Yes Program Yes Erase Yes
* Emulation protection *
Yes
Yes
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16.8.3
Error Protection
In error protection, an error is detected when SH7018 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the SH7018 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. Immediately after exception processing (excluding a reset) during programming/erasing 3. When a SLEEP instruction (including software standby) is executed during programming/erasing 4. When the bus is released during programming/erasing Error protection is released only by a power-on reset and in hardware standby mode. Figure 16.14 shows the flash memory state transition diagram.
355
Program mode Erase mode
RES = 0
Reset or standby (hardware protection)
RD VF PR ER FLER = 0
Error occurrence (Standby) RES = 0
RD VF PR ER FLER = 0
FLMCR1, EBR1, EBR2 initialization state
Error occurrence
RES = 0
Error protection mode
Standby mode Standby mode release
Error protection mode (Standby)
RD VF PR ER FLER = 1
RD VF PR ER FLER = 1
FLMCR1, EBR1, EBR2 initialization state
Legend RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible
RD: VF: PR: ER:
Memory read not possible Verify-read not possible Programming not possible Erasing not possible
Figure 16.14 Flash Memory State Transitions
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16.9
Flash Memory Emulation in RAM
Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 16.15 shows an example of emulation of real-time flash memory programming.
Start emulation program
Set RAMER
Write tuning data to overlap RAM
Execute application program
No
Tuning OK? Yes Clear RAMER
Write to flash memory emulation block
End of emulation program
Figure 16.15 Flowchart for Flash Memory Emulation in RAM
357
H'000000
Flash memory EB0 to EB3
H'004000 H'0043FF H'005000 H'0053FF H'006000 H'0063FF H'007000 H'0073FF H'008000
EB4 EB5 EB6 EB7
(1 kB) (3 kB) (1 kB) (3 kB) (1 kB) (3 kB) (1 kB) (3 kB)
This area can be accessed from both the RAM area and flash memory area
H'FFFFF800 Flash memory EB8 to EB10 On-chip RAM H'FFFFFBFF
H'027FFF
Figure 16.16 Example of RAM Overlap Operation Example in Which Flash Memory Block Area (EB4) is Overlapped 1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 0, to overlap part of RAM (H'FFFFF800 to H'FFFFFBFF) onto the area (part of EB4: H'004000 to H'0043FF) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB4). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM1 and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0.
358
2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used.
16.10
Note on Flash Memory Programming/Erasing
In the on-board programming modes (user mode and user program mode), NMI input should be disabled to give top priority to the program/erase operations (including RAM emulation).
16.11
Flash Memory Programmer Mode
Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 16.10 shows the pin settings for programmer mode. For the pin names in programmer mode, see section 1.3.2, Pin Functions.) Table 16.10 Programmer Mode Pin Settings
Pin Names Mode pins: MD3, MD2, MD1, MD0 FWE pin RES pin XTAL, EXTAL pins Settings MD3 = 1, MD2 = 1, MD1 = 0, MD0 = 1 High level input (in auto-program and auto-erase modes) Power-on reset circuit Oscillator circuit
Note: In programmer mode, the FWP pin has its polarity reversed and functions as the FWE (flash write enable) pin.
359
16.11.1
Socket Adapter Pin Correspondence Diagram
Connect the socket adapter to the chip as shown in figure 16.18. This will enable conversion to a 32-pin arrangement. The on-chip ROM memory map is shown in figure 16.17, and the socket adapter pin correspondence diagram in figure 16.18.
Addresses in MCU mode H'00000000
Addresses in programmer mode H'00000
On-chip ROM space 160 kB
H'00027FFF
H'27FFF
Figure 16.17 On-Chip ROM Memory Map
360
HD64F7018 (100 Pins) Pin No. 2 3 4 5 6 7 9 10 11 12 13 14 16 17 18 19 20 26 42 44 37 53 54 56 58 59 60 61 62 70 15,30,39,45,52,55,67,69,72,73, 74,79,99,100 1,8,22,25,32,43,57,65,71,76,89, 96 66 68 51 Other than the above VCC * VSS XTAL EXTAL RES N.C. (OPEN) Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE OE WE D7 D6 D5 D4 D3 D2 D1 D0 FWE
Socket Adapter (Conversion to 32Pin Arrangement)
HN28F101P (32 Pins) Pin No. 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 22 24 31 21 20 19 18 17 15 14 13 1 32 16 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE OE WE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 FWE VCC VSS
Oscillator circuit Power-on reset circuit
Legend A0 to A17 : Address input I/O0 to I/O7 : Data input/output : Chip enable CE : Output enable OE : Write enable WE : Flash write enable FWE
Note: * Includes NMI as well as MD0, MD1, MD2, and MD3.
Figure 16.18 Socket Adapter Pin Correspondence Diagram
361
16.11.2
Programmer Mode Operation
Table 16.11 shows how the different operating modes are set when using programmer mode, and table 16.12 lists the commands used in programmer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 16.11 Settings for Various Operating Modes In Programmer Mode
Pin Names Mode Read Output disable Command write Chip disable FWE H or L H or L H or L H or L CE L L L H OE L H H X WE H H L X I/O0 to I/O7 Data output Hi-Z Data input Hi-Z A0 to A17 Ain Ain *Ain Ain
Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. *Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin.
362
Table 16.12 Programmer Mode Commands
Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address Data X X X X H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address Data RA WA X X Dout Din H'20 H'71
Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n).
16.11.3
Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Table 16.13 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Notes
363
Command write A17 to A0 tces CE tceh tnxtc
Memory read mode Address stable
OE tf WE
twep tr
tds I/O7 to I/O0
tdh
Note: Data is latched on the rising edge of WE.
Figure 16.19 Timing Waveforms for Memory Read after Command Write Table 16.14 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Notes
364
Memory read mode A17 to A0 Address stable tnxtc CE
Another mode command write
tces
tceh
OE tf WE
twep tr
tds I/O7 to I/O0
tdh
Note: Do not enable WE and OE at the same time.
Figure 16.20 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 16.15 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol t acc t ce t oe t df t oh Min -- -- -- -- 5 Max 20 150 150 100 -- Unit s ns ns ns ns Notes
A17 to A0
Address stable
Address stable
CE OE WE
VIL
VIL VIH tacc toh tacc toh
I/O7 to I/O0
Figure 16.21 CE and OE Enable State Read Timing Waveforms
365
A17 to A0 CE
Address stable tce toe
Address stable tce toe
OE WE tacc toh I/O7 to I/O0 tdf tacc toh
VIH
tdf
Figure 16.22 CE and OE Clock System Read Timing Waveforms 16.11.4 Auto-Program Mode
1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 16.23). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end identification pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE.
366
Table 16.16 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t wsts t spa t as t ah t write t pns t pnh tr tf Min 20 0 0 50 50 70 1 -- 0 60 1 100 100 -- -- Max -- -- -- -- -- -- -- 150 -- -- 3000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns Notes
FWE
tpnh Address stable
A17 to A0
tpns tces tceh tnxtc
tnxtc
CE
OE
tf
twep
tr
tas
tah
Data transfer 1 to 128byte
twsts
tspa
WE
tds tdh twrite
Write operation complete verify signal
I/O7
I/O6 I/O5 to I/O0
Write normal complete verify signal
H'40
H'00
Figure 16.23 Auto-Program Mode Timing Waveforms
367
16.11.5
Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end identification pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Table 16.17 AC Characteristics in Auto-Erase Mode (Conditions: V CC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t ests t spa t erase t ens t enh tr tf Min 20 0 0 50 50 70 1 -- 100 100 100 -- -- Max -- -- -- -- -- -- -- 150 40000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Notes
368
FWE
A17 to A0
CE
OE WE
I/O7
;;;;
tenh tens tces tceh tnxtc tnxtc tf twep tr tests tspa tds tdh terase
Erase complete verify signal Erase normal complete verify signal
I/O6 I/O5 to I/O0
H'20
H'20
H'00
Figure 16.24 Auto-Erase Mode Timing Waveforms
369
16.11.6
Status Read Mode
1. Status read mode is provided to specify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 16.18 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Symbol Min 20 0 0 50 50 70 -- -- -- -- -- Max -- -- -- -- -- -- Unit s ns ns ns ns ns Notes
Read time after command write t nxtc CE hold time CE setup time Data hold time Data setup time Write pulse width t ceh t ces t dh t ds t wep t oe
OE output delay time Disable delay time CE output delay time WE rise time WE fall time
A17 to A0
;;;;
150 100 150 30 30 ns ns ns ns ns t df t ce tr tf
tces tceh tnxtc tces tceh tnxtc tnxtc
CE
tce
OE
tf
twep
tr
tf
twep
tr
toe
WE
tds
tdh
tds
tdh
tdf
I/O7 to I/O0
H'71
H'71
Note: I/O2 and I/O3 are undefined.
Figure 16.25 Status Read Mode Timing Waveforms
370
Table 16.19 Status Read Mode Return Commands
Pin Name I/O7 Attribute
I/O6
I/O5
Programming error
I/O4
Erase error
I/O3
--
I/O2
--
I/O1
I/O0
Normal Command end error identification 0 Command Error: 1
ProgramEffective ming or address error erase count exceeded 0 0
Initial value 0 Indications Normal end: 0 Abnormal end: 1
0 Programming
0 Erasing
0 --
0 --
Error: 1 Otherwise: 0 Error: 1 Otherwise: 0 Otherwise: 0
Count Effective exceeded: 1 address Otherwise: 0 Error: 1 Otherwise: 0
Note: I/O2 and I/O3 are undefined at present.
16.11.7
Status Polling
1. I/O7 status polling is a flag that indicates the operating status in auto-program/auto-erase mode. 2. I/O6 status polling is a flag that indicates a normal or abnormal end in auto-program/auto-erase mode. Table 16.20 Status Polling Output Truth Table
Pin Name I/O7 I/O6 I/O0 to I/O5 During Internal Operation 0 0 0 Abnormal End 1 0 0 0 1 0 Normal End 1 1 0
16.11.8
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 16.21 Stipulated Transition Times to Command Wait State
Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol t osc1 t bmv t dwn Min 30 10 0 Max -- -- -- Unit ms ms ms
371
tOSC1 VCC
tbmv
Memory read mode Command wait state Command Automatic write mode Normal/abnormal wait state Automatic erase mode complete verify
tdwn
RES
FWE
Note : For the level of FWE input pin, set VIL when using other than the automatic write mode and automatic erase mode.
Figure 16.26 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 16.11.9 Notes On Memory Programming
1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks.
372
Section 17 RAM
17.1 Overview
The SH7018 has 4 kbytes of on-chip RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus (figure 17.1). The CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. On-chip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. The contents of the onchip RAM are held in sleep mode. Memory area addresses H'FFFFE000 to H'FFFFFFFF are allocated to the on-chip RAM.
Internal data bus (32 bits)
H'FFFFF000 H'FFFFF004
H'FFFFF001 H'FFFFF005
H'FFFFF002 H'FFFFF006
H'FFFFF003 H'FFFFF007
On-chip RAM
H'FFFFFFFC
H'FFFFFFFD
H'FFFFFFFE
H'FFFFFFFF
Figure 17.1 Block Diagram of RAM
373
374
Section 18 Power-Down State
18.1 Overview
In the power-down state, the CPU functions are halted. This enables a great reduction in power consumption. 18.1.1 Power-Down States
The power-down state is effected by the following two modes: * Sleep mode * Standby mode Table 18.1 describes the transition conditions for entering the modes from the program execution state as well as the CPU and peripheral function status in each mode and the procedures for canceling each mode.
375
Table 18.1 Power-Down State Conditions
State Entering Mode Procedure On-Chip Peripheral CPU Modules Registers RAM Run Held Held I/O Ports Held Canceling Procedure * * * Halt* 1 Held or * high * impe2 dance* Interrupt DMAC address error Power-on reset NMI interrupt Power-on reset
Clock CPU Halt
Sleep Execute SLEEP Run instruction with SBY bit set to 0 in SBYCR
Stand- Execute SLEEP Halt by instruction with SBY bit set to 1 in SBYCR
Halt
Held
Held
SBYCR: standby control register. SBY: standby bit Notes: 1. Some bits within on-chip peripheral module registers are initialized by the standby mode; some are not. Refer to table 18.3, Register States in the Standby Mode, in section 18.4.1, Transition to Standby Mode. Also refer to the register descriptions for each peripheral module. 2. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of the SBYCR. Refer to section 18.2, Standby Control Register (SBYCR). For pin status other than for the I/O port, refer to Appendix B, Pin Status.
18.1.2
Related Register
Table 18.2 shows the register used for power-down state control. Table 18.2 Related Register
Name Standby control register Abbreviation SBYCR R/W R/W Initial Value H'1F Address H'FFFF8614 Access Size 8, 16, 32
376
18.2
Standby Control Register (SBYCR)
The standby control register (SBYCR) is a read/write 8-bit register that sets the transition to standby mode, and the port status in standby mode. The SBYCR is initialized to H'1F when reset.
Bit: 7 SBY Initial value: R/W: 0 R/W 6 HIZ 0 R/W 5 -- 0 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R
* Bit 7--Standby (SBY): Specifies transition to the standby mode. The SBY bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (TME) of the WDT timer control/status register (TCSR) is set to 1). To enter the standby mode, always halt the WDT by 0 clearing the TME bit, then set the SBY bit.
Bit 7: SBY 0 1 Description Executing SLEEP instruction puts the LSI into sleep mode Executing SLEEP instruction puts the LSI into standby mode (Initial value)
* Bit 6--Port High Impedance (HIZ): In the standby mode, this bit selects whether to set the I/O port pin to high impedance or hold the pin status. The HIZ bit cannot be set to 1 when the TME bit of the WDT timer control/status register (TCSR) is set to 1. When making the I/O port pin status high impedance, always clear the TME bit to 0 before setting the HIZ bit.
Bit 6: HIZ 0 1 Description Holds pin status while in standby mode Keeps pin at high impedance while in standby mode (Initial value)
* Bits 5 to 0--Reserved: Bit 5 is always reads as 0. The write value should always be 0. Bits 4 to 0 are always read as 1. The write value should always be 0.
18.3
18.3.1
Sleep Mode
Transition to Sleep Mode
Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the program execution state to the sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run during the sleep mode.
377
18.3.2
Canceling Sleep Mode
Sleep mode is canceled by an interrupt, DMAC address error, or power-on reset. Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt exception processing is executed. The sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU's status register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module. Cancellation by a DMAC Address Error: If a DMAC address error occurs, the sleep mode is canceled and DMAC address error exception processing is executed. Cancellation by a Power-On Reset: A power-on reset resulting from setting the RES pin to low level cancels the sleep mode.
18.4
18.4.1
Standby Mode
Transition to Standby Mode
To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction. The LSI moves from the program execution state to the standby mode. In the standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the prescribed voltages are applied. The register contents of some on-chip peripheral modules are initialized, but some are not (table 18.3). The I/O port status can be selected as held or high impedance by the port high impedance bit (HIZ) of the SBYCR. For pin status other than for the I/O port, refer to Appendix B, Pin Status.
378
Table 18.3 Register States in the Standby Mode
Module Interrupt controller (INTC) Cache memory (CAC) Bus state controller (BSC) Registers Initialized -- -- -- DMA channel control registers 0 and 1 (CHCR0, CHCR1) DMA operation register (DMAOR) Registers that Retain Data All registers All registers All registers -- Registers with Undefined Contents -- -- -- * DMA source address registers 0 and 1 (SAR0, SAR1) DMA destination address registers 0 and 1 (DAR0, DAR1) DMA transfer count registers 0 and 1 (DMATCR0, DMATCR1)
Direct memory access * controller (DMAC) *
*
*
Multifunction timer pulse unit (MTU) Watchdog timer (WDT)
MTU associated registers * Bits 7 to 5 (OVF, WT/IT, TME) of the timer control status register (TCSR)
-- * Bits 2 to 0 (CKS2 to CKS0) of the TCSR Timer counter (TCNT)
-- --
*
Reset control/status register * (RSTCSR)
Serial communication interface (SCI)
* * * * * *
Receive data register (RDR) -- Transmit data register (TDR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Bit rate register (BBR) -- --
--
A/D converter (A/D) Compare match timer (CMT)
All registers All registers
-- -- 379
Table 18.3 Register States in the Standby Mode (cont)
Module Pin function controller (PFC) I/O port (I/O) Power-down state related Registers Initialized -- -- -- Registers that Retain Data All registers All registers Registers with Undefined Contents -- --
Standby control -- register (SBYCR)
18.4.2
Canceling the Standby Mode
The standby mode is canceled by an NMI interrupt or a power-on reset. Cancellation by an NMI: Clock oscillation starts when a rising edge or falling edge (selected by the NMI edge select bit (NMIE) of the interrupt control register (ICR) of the INTC) is detected in the NMI signal. This clock is supplied only to the watchdog timer (WDT). A WDT overflow occurs if the time established by the clock select bits (CKS2 to CKS0) in the TCSR of the WDT elapses before transition to the standby mode. The occurrence of this overflow is used to indicate that the clock has stabilized, so the clock is supplied to the entire chip, the standby mode is canceled, and NMI exception processing begins. When canceling standby mode with NMI interrupts, set the CKS2 to CKS0 bits so that the WDT overflow period is longer than the oscillation stabilization time. When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level upon entering standby (when the clock is halted) is high level, and that the NMI pin level upon returning from standby (when the clock starts after oscillation stabilization) is low level. When canceling standby mode with an NMI pin set for rising edge, be sure that the NMI pin level upon entering standby (when the clock is halted) is low level, and that the NMI pin level upon returning from standby (when the clock starts after oscillation stabilization) is high level. Cancellation by a Power-On Reset: A power-on reset caused by setting the RES pin to low level cancels the standby mode.
380
18.4.3
Standby Mode Application Example
This example describes a transition to standby mode on the falling edge of an NMI signal, and a cancellation on the rising edge of the NMI signal. The timing is shown in figure 18.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) of the ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by an NMI exception service routine, the standby bit (SBY) of the SBYCR is set to 1, and a SLEEP instruction is executed, standby mode is entered. Thereafter, standby mode is canceled when the NMI pin is changed from low to high level. After the NMI pin is changed to high level, this level should be held until NMI exception handling begins.
Oscillator
CK
NMI
NMIE
SBY Oscillation settling time
NMI Exception exception service processing routine SBY = 1 SLEEP instruction
Standby Oscillation mode start time
WDT time set
NMI exception processing
Figure 18.1 Standby Mode NMI Timing (Application Example)
381
382
Section 19 Electrical Characteristics
19.1 Absolute Maximum Ratings
The absolute maximum ratings are listed in table 19.1. Table 19.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage (except A/D ports) Input voltage (A/D ports) Analog power supply voltage Analog input voltage Operating temperature Write/Erase temperature Storage temperature Symbol VCC Vin Vin AVCC VAN Topr Twe Tstg Value -0.3 to +4.3 -0.3 to VCC+0.3 -0.3 to AVCC+0.3 -0.3 to +4.3 -0.3 to AVCC+0.3 -20 to +75 0 to +70 -55 to +125 Unit V V V V V C C C
Note: Permanent damage to the chip may result if the absolute maximum ratings are exceeded.
383
19.2
DC Characteristics
The DC characteristics are listed in table 19.2. Table 19.2 DC Characteristics Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Input high-level RES, NMI voltage FWP EXTAL A/D ports PD0 to PD7, PA3, PA4, PB8 Other input pins (except for Schmitt trigger) Input low-level RES, NMI voltage FWP PD0 to PD7, PA3, PA4, PB8 Other input pins Schmitt-trigger PA2, PA5, PE0, input voltage PE2 V V
+ T - T + T + T - T - T
Symbol Min VIH
Typ Max PVCC + 0.3 VCC + 0.3 VCC + 0.3 AVCC + 0.3 PVCC + 0.3 VCC + 0.3
Unit Test Conditions V V V V V V
PVCC - 0.7 -- VCC - 0.3 VCC x 0.9 -- --
VCC x 0.75 -- 2.2 VCC x 0.75 --
VIL
-0.3 -0.3 -0.3 -0.3 4.0
-- -- -- -- -- --
0.5 VCC x 0.1 0.8 VCC x 0.2 -- 1.0 -- --
V V V V V V V V
V -V PA6 to PA9, PE4 to PE14 V -V
0.4 0.2
-- --
384
Table 19.2 DC Characteristics (cont) Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Input leakage current RES, NMI, FWP, PA2, PA5 to PA9, PE0, PE2, PE4 to PE14 A/D ports Other input pins Three-state A21 to A0, leakage current D7 to D0, (off state) CS3 to CS0, WRL, RD, ports A and E Output highlevel voltage |ITSI| Symbol Min |Iin| -- Typ Max -- 1.0 Unit Test Conditions A Vin = 0.5 to VCC-0.5V
-- -- --
-- -- --
1.0 1.0 1.0
A Vin = 0.5 to AVCC-0.5V A Vin = 0.5 to VCC-0.5V A Vin = 0.5 to VCC-0.5V
PE0, PE2, VOH PD0 to PD7, PA2 to PA5, PB8
PVCC - 0.7 PVCC - 1.0
--
--
V
I OH = -200 A
--
-- -- -- 0.4
V V V V
I OH = -1mA I OH = -200 A I OH = -1mA I OL = 1.6mA
Other output pins
VCC - 0.7 -- VCC - 1.0 --
Output lowlevel voltage
PE0, PE2, VOL PD0 to PD7, PA2 to PA5, PB8 Other output pins
--
--
--
--
0.6
V
I OL = 1.6mA
385
Table 19.2 DC Characteristics (cont) Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Input capacitance RES NMI All other input pins Current consumption Normal operation I CC Sleep mode Standby mode Symbol Min Cin -- -- -- -- -- -- -- Analog power supply current AI CC -- Typ -- -- -- 80 70 5 -- 5 Max 80 50 20 110 95 50 300 10 Unit pF pF pF mA mA A A mA Test Conditions Vin = 0 V f = 1 MHz Ta = 25C f = 20 MHz f = 20 MHz Ta 50C 50C < Ta f = 20 MHz
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Connect the AVCC pin to VCC and the AVSS pin to VSS . 2. Current consumption values are for conditions of VIHmin = VCC -0.5 V and VILmin = 0.5 V with all output pins unloaded.
Table 19.3 Permissible Output Current Values Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol I OL IOL -I OH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2.0 80 2.0 25 Unit mA mA mA mA
Note: To ensure chip reliability, do not exceed the output current values in table 19.3.
386
19.3
19.3.1
AC Characteristics
Clock Timing
The clock timing is shown in table 19.4. Table 19.4 Clock Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Operating frequency Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby recovery oscillation settling time Symbol f OP t cyc t CL t CH t Cr t Cf f EX t EXcyc t EXL t EXH t EXr t EXf t OSC1 t OSC2 Min 4 50 15 15 -- -- 4 50 17.5 17.5 -- -- 10 10 Max 20 250 -- -- 5 5 20 250 -- -- 5 5 -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms Figure 19.3 Figure 19.2 Figure Figure 19.1
tcyc tCH tCL
CK
1/2 VCC tCF
1/2 VCC tCR
Figure 19.1 System Clock Timing
387
tEXcyc tEXH tEXL VIH 1/2VCC tEXr
EXTAL
1/2VCC
VIH
VIH VIL tEXf VIL
Figure 19.2 EXTAL Clock Input Timing
CK
VCC
VCC min tOSC1 tOSC2
RES
Figure 19.3 Oscillation Settling Time
388
19.3.2
Control Signal Timing
Table 19.5 Control Signal Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item RES rise and fall RES pulse width NMI rise and fall RES setup time* NMI setup time* IRQ7, IRQ6, and IRQ3 to IRQ0 setup time* (edge detection) IRQ7, IRQ6, and IRQ3 to IRQ0 setup time* (level detection) NMI hold time IRQ7, IRQ6, and IRQ3 to IRQ0 hold time Symbol t RESr, t RESf t RESW t NMIr, t NMIf t RESS t NMIS t IRQES t IRQLS t NMIH t IRQEH Min -- 40 -- 35 35 35 35 35 35 Max 200 -- 200 -- -- -- -- -- -- Unit ns t cyc ns ns ns ns ns ns ns Figure 19.5 Figure 19.4, Figure 19.5 Figure Figure 19.4
Note: * The RES, NMI, IRQ7, IRQ6, and IRQ3 to IRQ0 signals are input asynchronously. If the setup time indicated is maintained, the clock rise (in the case of RES) or fall (in the case of NMI, IRQ7, IRQ6, and IRQ3 to IRQ0) will be recognized as a change in level. If the setup time indicated is not maintained, the change may not be recognized until the next clock rise or fall.
CK
tRESf tRESS VIH RES VIL tRESW VIL
tRESr tRESS VIH
Figure 19.4 Reset Input Timing
389
CK
tNMIH NMI tIRQEH IRQ edge
tNMIS VIH VIL tIRQES VIH VIL tIRQLS
IRQ level VIL
Figure 19.5 Interrupt Signal Input Timing
390
19.3.3
Bus Timing
Table 19.6 Bus Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Address delay time CS delay time 1 CS delay time 2 Read strobe delay time 1 Read strobe delay time 2 Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write data delay time Write data hold time WAIT setup time WAIT hold time Symbol t AD t CSD1 t CSD2 t RSD1 t RSD2 t RDS * 4 t RDH t WSD1 t WSD2 t WDD t WDH t WTS t WTH Min 3
*3
Max 25 21 21 18 18 -- -- 18 18 35 20*2 -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8
3*3 3*3 3*3 3*3 20 0 3*3 3*3 -- 0 20 0
391
Table 19.6 Bus Timing (cont) Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Read data access time Symbol t ACC
*1
Min
Max
Unit ns
Figure Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8
t cyc x -- (n* 5 + 2) - 50 t cyc x (n* 5 + 1.5) - 50 0 0 0 --
Access time from read strobe
t OE*1
ns
Write address setup time Write address hold time Write data hold time Notes: 1. 2. 3. 4. 5.
t AS t WR t WRH
-- -- --
ns ns ns
Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8 Figure 19.6 to figure 19.8
The t RDS specification needs not be met as long as the access time specification is met. t WDH (max) is a reference value. The minimum (min) values for delay times are reference (typical) values. t RDS is a reference value. The n is the wait number.
392
T1 CK tAD A21 to A0 tCSD1 CSn tRSD1 RD (read) tACC D7 to D0 (read) tWSD1 WRL (write) tAS tOE
T2
tCSD2
tRSD2
tRDS
tRDH
tWSD2
tWR
tWRH tWDD tWDH
D15 to D0 (write) Note: tRDH: Specified from the fastest negate timing of A21 to A0, CSn, or RD.
Figure 19.6 Basic Cycle (No Wait)
393
T1
TW
T2
CK tAD A21 to A0 tCSD1
tCSD2
CSn tRSD1 RD (read) tACC D7 to D0 (read) tWSD1 WRL (write) tAS tWDD D7 to D0 (write) tWRH tWDH tWSD2 tWR tRDS tRDH tOE tRSD2
Note: tRDH: Specified from the fastest negate timing of A21 to A0, CSn, or RD.
Figure 19.7 Basic Cycle (Software Wait)
394
T1
TW
TW
TW0
T2
CK
A21 to A0
CSn
RD (read)
D7 to D0 (read)
WRL (write)
D7 to D0 (write) tWTS WAIT tWTH tWTS tWTH
Figure 19.8 Basic Cycle (Wait Using Two Software Waits + WAIT Signal)
395
19.3.4
Multifunction Timer Pulse Unit Timing
Table 19.7 shows the multifunction timer pulse unit timing. Table 19.7 Multifunction Timer Pulse Unit Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Output compare output delay time Input capture input setup time Symbol t TOCD t TICS Min -- 30 Max 100 -- Unit ns ns Figure Figure 19.9
CK tTOCD Output compare output Input capture input
tTICS
Figure 19.9 MTU Input/Output Timing
396
19.3.5
I/O Port Timing
Table 19.8 shows the I/O port timing. Table 19.8 I/O Port Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Port output data delay time Port input hold time Port input setup time Symbol t PWD t PRH t PRS Min -- 100 100 Max 100 -- -- Unit ns ns ns Figure Figure 19.10
T1 CK tPRS Port (read) tPRH
T2
tPWD Port (write)
Figure 19.10 I/O Port Input/Output Timing
397
19.3.6
Serial Communication Interface Timing
Table 19.9 shows the serial communication interface timing. Table 19.9 Serial Communication Interface Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC = 3.0 to 3.6 V, AVCC VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C
Item Input clock cycle Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) Symbol t Scyc t Scyc t Sckw t Sckr t Sckf t TXD t RXS t RXH Min 4 6 0.4 -- -- -- 100 100 Max -- -- 0.6 1.5 1.5 100 -- -- Unit t cyc t cyc t Scyc t cyc t cyc ns ns ns Figure 19.12 Figure Figure 19.11
tSckw
tSckr
tSckf
SCK
tScyc
Figure 19.11 Input Clock Timing
398
tScyc SCK tTXD TXD (transmit data) tRXS tRXH RXD (receive data)
Figure 19.12 SCI Input/Output Timing (Synchronous Mode) 19.3.7 A/D Converter Timing
Table 19.10 shows the A/D converter timing. Table 19.10 A/D Converter Timing Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 0.5 V, PVCC VCC, AVCC VCC, f = 20 MHz, AVCC = 3.0 to 3.6 V, VSS = AVSS = 0V, Ta = -20 to +75C
Item A/D conversion start delay time Input sampling time CKS = 0 CKS = 1 CKS = 0 CKS = 1 A/D conversion time CKS = 0 CKS = 1 t CONV t SPL Symbol tD Min 10 6 - - 259 131 Typ - - 64 32 - - Max 17 9 - - 266 134 Unit t cyc Figure Figure 19.13
399
(1) CK
Address
(2)
Write signal
Input sampling timing
ADF tD tSPL t
CONV
(1): Write cycle of ADCSR (2): Address of ADCSR tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time
Figure 19.13 Analog Conversion Timing
400
19.3.8
Test Conditions for AC Characteristics
Input Reference Levels: High: 2.2 V, low: 0.8 V Output Reference Levels: High: 2.0 V, low: 0.8 V
IOL
LSI output pin CL
DUT output Vref
IOH CL is the total value including the capacitance of the testing jig. The settings for the different pins are as follows. 30 pF: CK, CS0 to CS3 50 pF: A21 to A0, D7 to D0, RD, WRL 70 pF: Port output pins other than those listed above and peripheral module output pins. IOL, IOH: Capacitance values are listed in section 19.2, DC Characteristics and table 19.3, Permissible Output Current Values.
Figure 19.14 Output Load Circuit
401
19.4
A/D Converter Characteristics
Table 19.11 A/D Converter Characteristics Conditions: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, AV CC VCC, VSS = AVSS = 0 V, Ta = -20 to +75C, CKS = 0
20.0MHz Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Reference values Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 13.4 20 1 5* 5* 5* 0.5* 6 Unit Bits s pF k LSB LSB LSB LSB LSB
402
Table 19.12 A/D Converter Characteristics Conditions: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, AV CC VCC, Vss = AVss = 0 V, Ta = -20 to +75C, CKS = 1
20MHz Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Reference values Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 6.7 20 1 5* 5* 5* 0.5* 6 Unit Bits s pF k LSB LSB LSB LSB LSB
403
404
Appendix A On-Chip Peripheral Module Registers
Table A.1 On-Chip Peripheral Module Registers
Bit Names Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI1
Address Register H'FFFFxxxx Name 81B0 81B1 81B2 81B3 81B4 81B5 8240 8241 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 826A 826B 826C 826D 826E 826F 8280 8281 8282 8284 8285 8286 8287 8288 8289 TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR0D TGR0C TGR0B TGR0A SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 TSTR TSYR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
-- -- CCLR2 -- -- -- TTGE --
-- -- CCLR1 -- IOB2 IOD2 -- --
-- -- CCLR0 BFB IOB2 IOD1 -- --
-- -- CKEG1 BFA IOB1 IOD0 TCIEV TCFV
-- -- CKEG0 MD3 IOA3 IOC3 TGIED TGFD
CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
All
MTU
ch0
-- -- IOB3 TTGE --
CCLR1 -- IOB2 -- --
CCLR0 -- IOB1 -- --
CKEG1 -- IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 -- --
TPSC2 MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
ch1
405
Table A.1
On-Chip Peripheral Module Registers (cont)
Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ch1 MTU
Address Register H'FFFFxxxx Name 828A 828B 82A0 82A1 82A2 82A4 82A5 82A6 82A7 82A8 82A9 82AA 82AB 8348 8349 834A 834B 834C 834D 834E 834F 8350 8351 8352 8353 8354 8355 8356 8357 8358 8359 835A 835B 8382 8383 PADRL ISR ICR IPRH IPRG IPRF IPRE IPRD IPRC IPRB IPRA TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR1B
-- -- IOB3 TTGE --
CCLR1 -- IOB2 -- --
CCLR0 -- IOB1 -- --
CKEG1 -- IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 -- --
TPSC2 MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
ch2
(IRQ0) (IRQ2) -- (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- -- (A/D) (CMT0) (WDT) -- NMIL IRQ0S -- IRQ0F
(IRQ0) (IRQ2) -- (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- -- (A/D) (CMT0) (WDT) -- -- IRQ1S -- IRQ1F
(IRQ0) (IRQ2) -- (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- -- (A/D) (CMT0) (TIM2) -- -- IRQ2S -- IRQ2F
(IRQ0) (IRQ2) -- (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- -- (A/D) (CMT0) (TIM2) -- -- IRQ3S -- IRQ3F
(IRQ1) (IRQ3) -- (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI) -- (CMT1) -- -- -- -- -- --
(IRQ1) (IRQ3) -- (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI) -- (CMT1) -- -- -- -- -- --
(IRQ1) (IRQ3) -- (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI) -- (CMT1) -- -- -- IRQ6S -- IRQ6F
(IRQ1) (IRQ3) -- (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI) -- (CMT1) -- -- NMIE IRQ7S -- IRQ7F PA8DR PA0DR
INTC
PA15DR PA14DR -- PA7DR PA6DR PA5DR
PA12DR PA11DR PA10DR PA9DR PA4DR PA3DR PA2DR PA1DR
I/O
Port A
406
Table A.1
On-Chip Peripheral Module Registers (cont)
Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA8IOR PA0IOR PA12MD Module PFC Port A
Address Register H'FFFFxxxx Name 8386 8387 838C 838D 838E 838F 8390 8391 8394 8395 8398 8399 839A 839B 8392 8393 8396 8397 839C 839D 83A2 83A3 83A6 83A7 83AC 83AD 83B0 83B1 83B3 83B4 83B5 83BA 83BB 83D0 83D1 CMSTR PECR2 PFDR PEIOR PEDR PDCRL PDIORL PDDRL PCCR PCIOR PCDR PBCR2 PBCR1 PBIOR PBDR PACRL2 PACRL1 PAIORL
PA15IOR PA14IOR -- PA7IOR -- -- PA6IOR PA5IOR
PA12IOR PA11IOR PA10IOR PA9IOR PA4IOR PA3IOR PA2IOR -- PA1IOR --
PA15MD -- PA11MD --
PA14MD --
PA10MD PA9MD1 PA9MD0 PA8MD1 PA8MD0 PA5MD -- -- PB2DR -- PB2IOR -- -- -- PB9DR PB1DR PB9IOR PB1IOR -- PA4MD -- PB8DR PB0DR PB8IOR PB0IOR -- PFC I/O Port B
PA7MD1 PA7MD0 PA6MD1 PA6MD0 -- -- -- PB7DR -- PB7IOR -- -- PA3MD -- PB6DR -- PB6IOR -- -- PA2MD1 PA2MD0 -- -- PB5DR -- PB5IOR -- -- -- PB4DR -- PB4IOR -- -- -- PB3DR -- PB3IOR --
PB9MD1 PB9MD0 PB8MD1 PB8MD0 -- PB1MD -- -- -- PB0MD PC8DR PC0DR I/O Port C
PB7MD1 PB7MD0 PB6MD1 PB6MD0 -- -- PB3MD -- -- --
PC15DR PC14DR PC13DR PC12DR PC11DR PC10DR PC9DR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR
PC15IOR PC14IOR PC13IOR PC12IOR PC11IOR PC10IOR PC9IOR PC8IOR PFC PC7IOR PC6IOR PC5IOR PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR PC15MD PC14MD PC13MD PC12MD PC11MD PC10MD PC9MD PC7MD -- PD7DR PC6MD -- PD6DR PC5MD -- PD5DR PC4MD -- PD4DR PC3MD -- PD3DR PC2MD -- PD2DR PC1MD -- PD1DR PC8MD PC0MD -- PD0DR I/O Port D
PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR TFC PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR -- PD7MD -- PE7DR PF7DR -- PD6MD -- PD5MD -- PD4MD -- PD3MD -- PD2MD -- PE2DR PF2DR -- PD1MD -- -- PF1DR -- PD0MD -- PE0DR PF0DR PE8IOR PE0IOR PE4MD PE0MD0 -- STR0 All CMT I/O PFC Port F Port E I/O Port E
PE14DR PE13DR PE12DR -- PE6DR PF6DR PE5DR PF5DR PE4DR PF4DR -- PF3DR
PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10OR PE9IOR PE7IOR -- -- -- -- PE6IOR PE7MD -- -- -- PE5IOR -- -- -- -- PE4IOR PE6MD PE3IOR -- PE2IOR PE5MD -- -- -- PE1IOR -- -- -- STR1
PE2MD0 -- -- -- -- --
407
Table A.1
On-Chip Peripheral Module Registers (cont)
Bit Names Bit 7 -- CMF CMCNT0 Bit 6 -- CMIE Bit 5 -- -- Bit 4 -- -- Bit 3 -- -- Bit 2 -- -- Bit 1 -- CKS1 Bit 0 -- CKS0 Module ch0 CMT
Address Register H'FFFFxxxx Name 83D2 83D3 83D4 83D5 83D6 83D7 83D8 83D9 83DA 83DB 83DC 83DD 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8580 8581 8582 8583 8610 8611 8612 8613 8614 8620 8621 8622 8623 BCR2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR FLMCR1 FLMCR2 EBR1 EBR2 TCSR TCNT RSTCSR RSTCSR SBYCR BCR1 CMCOR1 CMCNT1 CMCSR1 CMCOR0 CMCSR0
-- CMF
-- CMIE
-- --
-- --
-- --
-- --
-- CKS1
-- CKS0
ch1
AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE FWE FLER EB7 -- OVF
AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- SWE -- EB6 -- WI/IT
AD7 -- AD7 -- AD7 -- AD7 -- ADST -- ESU -- EB5 -- TME
AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSU -- EB4 -- --
AD5 -- AD5 -- AD5 -- AD5 -- CKS -- EV -- EB3 -- --
AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- PV -- EB2 EB10 CKS2
AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- E -- EB1 EB9 CKS1
AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- P -- EB0 EB8 CKS0
A/D
FLASH
WDT
WOVF WOVF SBY -- -- IW31 CW3
RSTE RSTE HIZ -- -- IW30 CW2
-- -- -- -- -- IW21 CW1
-- -- -- -- -- IW20 CW0
-- -- -- -- A3SZ IW11 SW3
-- -- -- -- A2SZ IW10 SW2
-- -- -- -- A1SZ IW01 SW1
-- -- -- -- A0SZ IW00 SW0 Power-Down State BSC
408
Table A.1
On-Chip Peripheral Module Registers (cont)
Bit Names Bit 7 -- -- RAMER -- -- T2CSR -- T2CNT -- CMF -- Bit 6 -- -- -- -- -- CMIE -- Bit 5 W31 W11 -- -- -- CKS2 -- Bit 4 W30 W10 -- -- -- CKS1 -- Bit 3 -- -- -- -- -- CKS0 -- Bit 2 -- -- -- RAMS -- -- -- Bit 1 W21 W01 -- RAM1 -- -- -- -- Bit 0 W20 W00 -- RAM0 -- TIM2 Module BSC
Address Register H'FFFFxxxx Name 8624 8625 8628 8629 862C 862D 862E 862F 8630 8631 T2COR WCR1
--
--
--
--
--
--
--
--
409
Appendix B Pin States
B.1 Pin States
Pin States after Reset and in Power-Down State
Pin State Pin Function Type Clock System control Interrupt Pin Name CK RES NMI IRQ0 to IRQ3, IRQ6, IRQ7 Address bus Data bus Bus control A0 to A21 D0 to D7 WAIT RD CS0 to CS3 WRH, WRL MTU TIOC0A, TIOC0C TIOC1A, TIOC1B TIOC2A, TIOC2B SCI TxD RxD A/D converter I/O ports AN0 to AN7 PA0 to PA15 PB0 to PB9 PC0 to PC15 PD0 to PD7 PE0, PE2, PE4 to PE14 Legend: I: input, O: output, H: high-level output, L: low-level output, Z: high impedance, K: high impedance for input pins and maintain status for output pins Z Z Z Z O I I K After Reset Power-On O I I Z O Z Z H H H Z Power-Down State Sleep O I I I O I/O I H H H I/O
Table B.1
410
B.2
Bus-Related Signals and Pin States
Bus-Related Signals and Pin States
On-Chip Peripheral Modules On-Chip RAM Space H H H H H H H Address Z 16-Bit Space 8-Bit Space H H H H H H H Address Z Upper Bytes H H H H H H H Address Z Lower Bytes H H H H H H H Address Z Word/ Upper Longword Bytes H H H H H H H Address Z Enabled L H H L H H Address Z Normal External Space 16-Bit Space Lower Bytes Enabled L H H H H L Address Data Word/ Longword Enabled L H H L H L Address Data
Table B.2
Pin Name CS0 to CS3 RD R W WRH R W WRL R W A21 to A0 D7 to D0
Legend: R: read, W: write, H: high-level output, L: low-level output, Z: high impedance, Enabled: chip select signal corresponding to area being accessed is low-level, otherwise chip select signal is high-level
411
Appendix C Product Lineup
Table C.1 SH7018 Product Lineup
Voltage 3.3 V Operating Frequency 20 MHz Marking Code HD64F7018X20 Package TFP-100B
Product Name SH7018
412
Appendix D Package Dimensions
Figure D.1 shows the TFP-100B package dimensions of the SH7018.
Unit: mm
16.0 0.2 14 75 76 51 50
16.0 0.2
100 1 *0.22 0.05 0.20 0.04 25 0.08 M 1.0
26
0.5
*0.17 0.05 0.15 0.04
1.00
1.20 Max
1.0 0 - 8 0.5 0.1
0.10
0.10 0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TFP-100B -- Conforms 0.5 g
Figure D.1 Package Dimensions (TFP-100B)
413
414
SH7018 Hardware Manual
Publication Date: 1st Edition, July 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.

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